Patents by Inventor Rob B. Kerr

Rob B. Kerr has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory cell arrays
    Patent number: 7045834
    Abstract: A memory device includes memory cells, bit lines, active area lines running generally in parallel to the bit lines, and transistors formed in each active area line and electrically coupling memory cells to corresponding bit lines. Each bit line includes slanted portions that intersect a corresponding portion of an active area line at an angle. Contacts electrically coupling the bit line to portions of the active area line are formed in a region generally defined by the angled intersection of the bit line to the active area line. The memory cells can have an area of about 6F2, and the bit lines can be coupled to sense amplifiers in a folded bit line configuration. Each bit line includes a first level portion and a second level portion.
    Type: Grant
    Filed: January 29, 2002
    Date of Patent: May 16, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Luan Tran, D. Mark Duncan, Tyler A. Lowrey, Rob B. Kerr, Kris K. Brown
  • Method of making memory cell arrays
    Patent number: 6607944
    Abstract: A memory device includes memory cells, bit lines, active area lines running generally in parallel to the bit lines, and transistors formed in each active area line and electrically coupling memory cells to corresponding bit lines. Each bit line includes slanted portions that intersect a corresponding portion of an active area line at an angle. Contacts electrically coupling the bit line to portions of the active area line are formed in a region generally defined by the angled intersection of the bit line to the active area line. The memory cells can have an area of about 6F2, and the bit lines can be coupled to sense amplifiers in a folded bit line configuration. Each bit line includes a first level portion and a second level portion.
    Type: Grant
    Filed: July 30, 2001
    Date of Patent: August 19, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Luan Tran, D. Mark Duncan, Tyler A. Lowrey, Rob B. Kerr, Kris K. Brown
  • Memory cell arrays
    Publication number: 20030102515
    Abstract: A memory device includes memory cells, bit lines, active area lines running generally in parallel to the bit lines, and transistors formed in each active area line and electrically coupling memory cells to corresponding bit lines. Each bit line includes slanted portions that intersect a corresponding portion of an active area line at an angle. Contacts electrically coupling the bit line to portions of the active area line are formed in a region generally defined by the angled intersection of the bit line to the active area line. The memory cells can have an area of about 6F2, and the bit lines can be coupled to sense amplifiers in a folded bit line configuration. Each bit line includes a first level portion and a second level portion.
    Type: Application
    Filed: January 29, 2002
    Publication date: June 5, 2003
    Inventors: Luan Tran, D. Mark Durcan, Tyler A. Lowrey, Rob B. Kerr, Kris K. Brown
  • Memory cell arrays comprising intersecting slanted portions
    Patent number: 6410948
    Abstract: A memory device includes memory cells, bit lines, active area lines running generally in parallel to the bit lines, and transistors formed in each active area line and electrically coupling memory cells to corresponding bit lines. Each bit line includes slanted portions that intersect a corresponding portion of an active area line at an angle. Contacts electrically coupling the bit line to portions of the active area line are formed in a region generally defined by the angled intersection of the bit line to the active area line. The memory cells can have an area of about 6F2, and the bit lines can be coupled to sense amplifiers in a folded bit line configuration. Each bit line includes a first level portion and a second level portion.
    Type: Grant
    Filed: June 28, 1999
    Date of Patent: June 25, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Luan Tran, D. Mark Duncan, Tyler A. Lowrey, Rob B. Kerr, Kris K. Brown