Abstract: A graphics accelerator architecture in which instructing on a data stream which includes a mixture of scalars and short vectors (i.e. 2-, 3- or 4-vectors) are defined with an argument in the opcode which specifies the data type(s) being manipulated. The sequencer expands each of these opcodes on the fly to produce an appropriate series of instructions for the scalar processor to execute. This is particularly advantageous with the limited set of vector lengths handled in rendering operations.

Abstract: A graphics memory architecture in which row addresses are permuted, in a basically tile-oriented storage architecture, so that fast parallel access is provided both by scanlines (for video operations) and also by tiles (for graphics operations).

Abstract: A 3D graphics accelerator in which vertex data is locally cached, at individual rendering subsystems, in circular buffers which are NOT large enough to hold the maximum number of data fields for the maximum number of vertices which can be parallel-processed. Instead, the circular buffers are preferably made large enough to hold the maximum number of data fields for a minimum useful number of vertices; the same buffers can also be used to hold a smaller number of data fields for the maximum number of vertices.

Abstract: A tile-oriented graphics processing system in which an additional level of caching is provided locally, at the output of a patch-processing graphics computation block. This additional local storage buffers the current tile, so that repeated accesses to the same tile can avoid pipelining delays connected with access to the main cache. (Even an on-chip cache, in a large chip, can impose access delays which are significant in relation to the computation speeds involved.

Abstract: A building block has a cement-based attachment layer on one or both exterior surfaces of the block that can receive and hold a penetrating fastener such as a nail, screw, staple, or the like. This allows surficial coverings such as wallboard, siding or other materials to be easily attached to a block wall made of the building blocks. The block includes substantially semi-cylindrical concave portions that form a cross-linked structure of channels when the blocks are assembled into a wall. Once the blocks have been stacked in place in a wall, grout or other suitable filling material is poured into the cross-linked structure of channels. When the filling material hardens, the blocks are locked together. Surficial covering materials may then be nailed, screwed, or stapled directly to the attachment layer.

Abstract: A concrete-based building block has an attached wooden attachment layer on one or both exterior surfaces of the block that can receive and hold a penetrating fastener such as a nail, screw, staple, or the like. This allows surficial coverings such as wallboard, siding or other materials to be easily attached to a block wall made of the building blocks. The block includes substantially semi-cylindrical concave portions that form a cross-linked structure of channels when the blocks are assembled into a wall. Once the blocks have been stacked in place in a wall, grout or other suitable filling material is poured into the cross-linked structure of channels. When the filling material hardens, the blocks are locked together. Surficial covering materials may then be nailed, screwed, or stapled directly to the attachment layer of the blocks.

Abstract: A graphics system using multiple processors which is able to fully support multi-processor operation using only PCI read operations between processors. Each of the graphics processors performs its operations on its respective scanlines, and writes to its own framebuffer, but the need for writes from one processor to the framebuffer of another processor is eliminated.

Abstract: A geometry and lighting graphics accelerator with an improved clipping process. Clipping is performed prior to any calculation or evaluation of primitives for lighting, texture, fog, or color. Barycentric coordinates are used to define all vertices: original, intermediate, and final intersection points. Use of barycentric coordinates results in less storage space. A circular buffer is used during the clipping process to store input and output polygons. Use of the circular buffer also results is reduced storage requirements.

Abstract: A system and method for computer graphics generation which uses a local library of graphics textures. When an application, run either locally or over a communications system, requires texture-mapped graphics, texture data is retrieved from the local library instead of transmitted to the system.

Abstract: A graphics processing chip which uses a deep pipeline of multiple asynchronous units to achieve a high net throughput in 3D rendering. Preferably reads and writes to a local buffer are provided by separate stages of the pipeline. Preferably some of the individual units include parallel paths internally. Preferably some of the individual units are connected to look ahead by more than one stage, to keep the pipeline filled while minimizing the use of expensive deep FIFOs.

Abstract: A concrete-based building block has an integrally-formed wooden attachment layer on one or both exterior surfaces of the block that can receive and hold a penetrating fastener such as a nail, screw, staple, or the like. This allows surficial coverings such as wallboard, siding or other materials to be easily attached to a block wall made of the building blocks. The block includes substantially semi-cylindrical concave portions that form a cross-linked structure of channels when the blocks are assembled into a wall. Once the blocks have been stacked in place in a wall, grout or other suitable filling material is poured into the cross-linked structure of channels. When the filling material hardens, the blocks are locked together. Surficial covering materials may then be nailed, screwed, or stapled directly to the attachment layer of the blocks.

Abstract: A graphics processing chip which uses a deep pipeline of multiple asynchronous units to achieve a high net throughput in 3D rendering. Preferably reads and writes to a local buffer are provided by separate stages of the pipeline. Preferably some of the individual units include parallel paths internally. Preferably some of the individual units are connected to look ahead by more than one stage, to keep the pipeline filled while minimizing the use of expensive deep FIFOs.

Abstract: A building block has a cement-based attachment layer on one or both exterior surfaces of the block that receives and holds a penetrating fastener such as a nail, screw, staple, or the like. This allows surficial coverings such as wallboard, siding or other materials to be easily attached to a block wall made of the building blocks. The block includes substantially semi-cylindrical concave portions that form a cross-linked structure of channels when the blocks are assembled into a wall. Once the blocks have been stacked in place in a wall, grout or other suitable filling material is poured into the cross-linked structure of channels. When the filling material hardens, the blocks are locked together. Surficial covering materials may then be nailed, screwed, or stapled directly to the attachment layer of the blocks.

Abstract: A 3D rendering accelerator, in which the hardware texturing capability is also used to provide enhanced 2D rendering. Texturing units, when operating in a 2D mode, are available for use for storing icons and characters locally to avoid the expense of doing a lookup from the host system. Texturing units are also used as storage for pattern data for performing a tiled fill of a graphical object and for defining arbitrarily large stipple patterns. Color index dither patterns may also be stored in the texture units to avoid the necessity of doing a texture download from the host system.

Abstract: A graphics processing system with a message-passing architecture, in which the rasterizer can be bypassed by a particular type of message from the host. This permits rasterization to be slaved to the host downloads and bitmasks, so that images and patterns can be applied to lines and polygons, rather than just rectangles as is the case for prior art.

Abstract: The preferred embodiment discloses a pipelined graphics processor in which the sequence can be dynamically reconfigured (e.g. between primitives) in a rendering sequence. The pipeline sequence can be configured for compliance with specifications such as OpenGL, but may also be optimized by reconfiguring the pipeline sequence to eliminate unnecessary processing. In a preferred embodiment, pixel elimination sequences such as depth and stencil tests are performed before texturing calculations are performed, so that unneeded pixel data is discarded before said texturing calculations are performed.

Abstract: A graphics subsystem using a smart DMA controller to perform DMA data loading with some modified addressing. The DMA controller can operate in an incremental mode, in a hold mode (where each chunk of data is written into the same address), or in an indexed mode. The buffer registers are assigned to groups, and, in the indexed mode, a header in the DMA buffer precedes any data for a group. The header identifies the recipient group and each register (in the group) to be updated has its corresponding bit set. Thus a high-efficiency DMA operation is obtained even in cases when increment mode cannot be used directly, e.g. when not all registers in a group need to be written, and/or the registers which need to be written are not contiguous.

Abstract: A rendering system with multi-pixel span processing capability. When 3D graphics processes are not required, 2D data is processed in multi-pixel span fragments. Span fragments permit parallel processing of multiple pixels in a serial architecture, and permit VRAM block fills for accelerated processing under optimal conditions.

Abstract: A 3D graphics system in which a pre-rendering stage is combined with a rendering stage. Any GUI window which is not completely displayed on-screen (because it extends past screen boundaries or is overlapped by other windows, etc.), is divided into at least two portions, e.g. rectangles, for scissoring operations. If a primitive appears at least partially in some rectangle, rendering setup data is calculated, then applied against each rectangle in which it appears for a scissoring operation, and the portion of the primitive in that rectangle which survives the scissor is then rendered. The rendering data is stored between each scissoring function, and is not recalculated. Any portion of the primitive which does not appear in a rectangle is not rendered, thereby eliminating any rendering overhead for any primitive which would be completely hidden anyway.

Abstract: A device and method for providing a frame buffer interface to a serial rendering system which automatically synchronizes with data in the rendering path before blanking the active frame. To prevent rewriting to a frame buffer of rendered data before the current rendered data can be displayed, the disclosed embodiment provides that when the data is ready to be displayed, all further writes to the buffer are suspended, while all other accesses throughout the system are allowed to proceed. When the vblank command is received, data is passed to the display system for display, and writes to that buffer are re-enabled. When writes to a specific buffer portion are suspended, all other processes may continue independently.