Abstract: Techniques for charging an electronic device using a Universal Serial Bus (USB) cable and connector are provided. In an example, an apparatus can include a charger, a USB cable coupled to the charger at a first end of the cable, a paddle card for a USB connector coupled to the cable at a second end of the cable, the paddle card including differential data contacts, and wherein the differential data contacts of the paddle card are shorted together at the paddle card.

Abstract: A paddle board includes an electronic marker circuit configured to indicate at least one capability of a cable assembly to a device coupled to the cable assembly and to select the device as one of a source or a sink, the paddle board being powered by the device, a register configured to store at least one variable value associated with at least one of the cable assembly and the paddle board, and a temperature sensor configured to sense a temperature of the paddle board and configured to store a value indicating the sensed temperature in the register.

Abstract: An exemplary system, method, and computer-accessible medium may be provided, which may include, for example, receiving a design a memory including a plurality MBIST logic paths and a plurality of non-MBIST logic paths, determining particular non-MBIST logic path(s) of the non-MBIST logic paths to deactivate, and deactivating only the particular non-MBIST logic path(s). The particular non-MBIST logic path(s) may be deactivated using a clock signal. A simulation on the memory may be performed while the particular non-MBIST logic path(s) may be deactivated. The particular non-MBIST logic path(s) may be reactivated after the simulation has been performed. The deactivating the particular non-MBIST logic path(s) may include forcing all flip flops in the particular non-MBIST logic path(s) to a known state.

Abstract: This document discusses, among other things, apparatus, systems, and methods to prevent a voltage of a charging battery from exceeding a voltage threshold, including receiving charging information from a battery and controlling an output current of a travel adapter, including adjusting the received battery current information using a load current to prevent the voltage of the battery from exceeding a voltage threshold, and providing output current limit information to the travel adapter using the adjusted battery current information.

Abstract: This document discusses, among other things, apparatus, systems, and methods to prevent a voltage of a charging battery from exceeding a voltage threshold, including receiving charging information from a battery and controlling an output current of a travel adapter, including adjusting the received battery current information using a load current to prevent the voltage of the battery from exceeding a voltage threshold, and providing output current limit information to the travel adapter using the adjusted battery current information.

Abstract: Systems and methods disclosed herein provide for improved diagnostics for memory built-in self-test (“MBIST”). Embodiments provide for a sequence iterator unit including a diagnostics analysis unit that monitors and reports on the failing read count associated with the tested memory. Embodiments further provide for a bit fail map report that is generated based on the failing read count.

Abstract: Embodiments relate generally to a scalable, modularized mechanism which allows for storing programmable data streams on chip and provides repeatable on-demand issuances of data streams to one or more targeted instruments. In some embodiments, multiple data streams are grouped into data stream schedules to perform a series of programmable operations on demand. In these and other embodiments, data stream schedules can be reused and further grouped into data stream plans that can be executed in any order upon request or are hard-coded in a specific order.

Abstract: An exemplary fuse control arrangement can be provided, which can include, for example, a fuse control unit(s), which includes a test access method interface(s) and a programmable memory(ies), wherein the fuse control unit(s) is configured to provide fuse information to repair a memory(ies). The fuse control unit(s) can be coupled to the memory(ies) and the memory(ies) can be coupled to a register repair unit(s). The fuse control unit(s) can provide the register repair unit(s) with the fuse information to repair the memory(ies).

Abstract: Systems and methods disclosed herein provide for improved diagnostics for memory built-in self-test (“MBIST”). Embodiments provide for a two-pass diagnostic test of the target memory, wherein, in the first pass, a data compare unit provides clock cycle values associated with detected mis-compares to a tester, and, in the second pass, the data compare unit extracts data vectors associated with the clock cycle values. Embodiments further provide for a bit fail map report that is generated based on the extracted data vectors.

Abstract: An exemplary system, method, and computer-accessible medium for modifying a memory unit(s) may be provided, which may include, for example, determining a location of a first memory built-in self-test (MBIST) logic(s) in the memory unit(s), removing the first MBIST logic(s) from the memory unit(s), and inserting a second MBIST logic(s) into the memory unit(s) at the location. The second MBIST logic(s) may be based on the first MBIST logic(s). The second MBIST logic(s) may be generated, which may be performed by modifying the first MBIST logic(s). The first MBIST logic(s) may be modified based on a modification(s) to a register transfer level (RTL) list associated with the memory unit(s). A pattern control file or a Test Data Register mapping file may be modified based on the modification to the first MBIST logic(s).

Abstract: An exemplary bitmap file can be provided, which can include, for example, a map of a cell array structure of a memory(ies), a plurality of memory values superimposed on the cell array structure based on a simulated testing of the memory(ies). The memory values may be values being written to the memory(ies) while the memory(ies) is being tested. The memory values may be values in a test pattern(s) being used to test the memory(ies). Each cell in the cell array structure can have a particular memory value superimposed thereon. A cell(s) in the cell array structure may be highlighted, which may correspond to an incorrect memory value.

Abstract: Computer system for programmable built-in self-test (PMBIST) insertion into system-on-chip designs comprising one or more memories, including at least one processor and computer-executable instructions that cause the system to determine a PMBIST configuration based on one or more test configuration files; generate one or more package files based on the PMBIST configuration; insert PMBIST hardware into the SoC design based on the package files and characteristics of the memories; suspend PMBIST hardware insertion after an event related to the package files; and resume PMBIST hardware insertion after receiving one or more updated package files. In some embodiments, the package files are independent of vendor-specific memory models. In some embodiments, the package files comprise a plurality of data structures. Exemplary methods and computer-readable media can also be provided embodying one or more procedures the system is configured to perform.

Abstract: A device includes an interface configured to couple a power source to the device. The interface includes a plurality of contacts including at least one first contact configured to couple a voltage bus of the power source to a voltage bus of the device, and at least one second contact configured to couple the voltage bus of the power source to a secondary bus of the device. The device further includes a detector configured to determine a contact resistance of the at least one first contact based on a first current associated with the voltage bus and a second current associated with the secondary bus.

Abstract: An exemplary memory arrangement can be provided, which can include, for example, a memory(ies), and an algorithmic memory unit(s) (AMU) coupled to the memory(ies), wherein the AMU includes a programmed testplan algorithm(s) configured to test the memory(ies). The AMU(s) can further include a hardwired testplan(s) configured to test the memory(ies). A Joint Test Action Group (“JTAG”) controller may be coupled to the AMU(s), which can be configured to access logic of the programmed testplan algorithm(s). A direct access controller (DAC) can be coupled to the AMU(s), which can be configured to access internal nodes in the AMU(s). The DAC can be configured to activate the programmed testplan algorithm(s) using a minimally direct access pin interface in the AMU(s).

Abstract: This document discusses, among other things, apparatus and methods to optimize charging of a battery, including providing a first charge profile configured to provide charge current pulses to a battery in a plurality of steps. In the first charge profile, the charge current pulses can be stepped down in the plurality of steps using a comparison of a terminal voltage of the battery to a clamp voltage. When the terminal voltage meets or exceeds the clamp voltage, a high time current of the charge current pulse can be decreased and the clamp voltage can be increased before providing a subsequent charge current pulse.

Abstract: A system and method automatically determines the physical memories inside a core or macro and their association with logical memories and their enabling signals. An integrated circuit (IC) source file that describes an integrated circuit in a hardware description language is received. The IC source file includes macros corresponding to memory. For each macro, a physical description file corresponding to the macro is generated. The description includes how the macro corresponds to the physical memory, associations of physical memories with the logical memory, enabling conditions, and data needed to test the memory.

Abstract: A paddle board includes an electronic marker circuit configured to indicate at least one capability of a cable assembly to a device coupled to the cable assembly and to select the device as one of a source or a sink, the paddle board being powered by the device, a register configured to store at least one variable value associated with at least one of the cable assembly and the paddle board, and a temperature sensor configured to sense a temperature of the paddle board and configured to store a value indicating the sensed temperature in the register.

Abstract: A power converter includes a load detector a processor and a power control block. The load detector is configured to determine a change in a load value of an electronic device coupled to the power converter without receiving a message communicated from the electronic device indicating the change in the load value, and determine if the change in the load value exceeds a threshold value. The processor, in response to determining the change in the load value exceeds the threshold value, is configured to signal the power converter to reduce a voltage. The power control block is configured to reduce the voltage based on the signal.

Abstract: A device includes an interface configured to couple a power source to the device. The interface includes a plurality of contacts including at least one first contact configured to couple a voltage bus of the power source to a voltage bus of the device, and at least one second contact configured to couple the voltage bus of the power source to a secondary bus of the device. The device further includes a detector configured to determine a contact resistance of the at least one first contact based on a first current associated with the voltage bus and a second current associated with the secondary bus.

Abstract: Method and apparatus for testing the memory components of an integrated Circuit (IC) using a routing logic and a built-in design for test (DFT) hardware processing device. Based on input provided from an interface controller to the IC, the IC is tested according to one of at least two modes. In a first mode, the built-in DFT hardware processing device executes a test that checks for faults in the physical memory of the IC. In a second mode, the built-in DFT hardware processing device executes a test that checks for faults in the error correction logic of the IC. By using the same routing logic and built-in DFT hardware processing device, tests of the memory components according to the first and second mode can be executed on an automatic and serial basis, even after the manufacture of the IC.