Patents by Inventor Robert A. Drehmel
Robert A. Drehmel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11074205Abstract: A snooper of a processing unit connected to processing units via a system fabric receives a first single bus command in a bus protocol that allows sampling over the system fabric of the capability of snoopers to handle an interrupt and returns a first response indicating the capability of the snooper to handle the interrupt. The snooper, in response to receiving a second single bus command in the bus protocol to poll a first selection of snoopers for an availability status to service a criteria specified in the second single bus command, returns a second response indicating the availability of the snooper to service the criteria. The snooper, in response to receiving a third single bus command in the bus protocol to direct the snooper to handle the interrupt, assigns the interrupt to a particular processor thread of a respective selection of the one or more separate selections of processors threads distributed in the processing unit.Type: GrantFiled: August 14, 2019Date of Patent: July 27, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Richard L. Arndt, Florian Auernhammer, Wayne M. Barrett, Robert A. Drehmel, Guy L. Guthrie, Michael S. Siegel, William J. Starke
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Patent number: 10565140Abstract: A technique for handling interrupts in a data processing system includes receiving, by an interrupt routing controller (IRC), an event routing message (ERM) that includes an event source number for a notification source with an unserviced interrupt. In response to receiving the ERM, the IRC builds an event notification message (ENM) based on the event source number. The IRC determines a scope for the ENM based on an event target group (ETG) associated with the event source number. The IRC issues the ENM to an interrupt presentation controller (IPC) at the scope associated with the ETG.Type: GrantFiled: November 29, 2017Date of Patent: February 18, 2020Assignee: International Business Machines CorporationInventors: Florian A. Auernhammer, Wayne M. Barrett, Robert A. Drehmel, Michael S. Siegel
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Patent number: 10552351Abstract: A technique for handling interrupts in a data processing system includes receiving, by an interrupt routing controller (IRC), an event routing message (ERM) that includes an event source number for a notification source with an unserviced interrupt. In response to receiving the ERM, the IRC builds an event notification message (ENM) based on the event source number. The IRC determines a scope for the ENM based on an event target group (ETG) associated with the event source number. The IRC issues the ENM to an interrupt presentation controller (IPC) at the scope associated with the ETG.Type: GrantFiled: January 22, 2019Date of Patent: February 4, 2020Assignee: International Business Machines CorporationInventors: Florian A. Auernhammer, Wayne M. Barrett, Robert A. Drehmel, Michael S. Siegel
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Publication number: 20190370198Abstract: A snooper of a processing unit connected to processing units via a system fabric receives a first single bus command in a bus protocol that allows sampling over the system fabric of the capability of snoopers to handle an interrupt and returns a first response indicating the capability of the snooper to handle the interrupt. The snooper, in response to receiving a second single bus command in the bus protocol to poll a first selection of snoopers for an availability status to service a criteria specified in the second single bus command, returns a second response indicating the availability of the snooper to service the criteria. The snooper, in response to receiving a third single bus command in the bus protocol to direct the snooper to handle the interrupt, assigns the interrupt to a particular processor thread of a respective selection of the one or more separate selections of processors threads distributed in the processing unit.Type: ApplicationFiled: August 14, 2019Publication date: December 5, 2019Inventors: RICHARD L. ARNDT, FLORIAN AUERNHAMMER, WAYNE M. BARRETT, ROBERT A. DREHMEL, GUY L. GUTHRIE, MICHAEL S. SIEGEL, WILLIAM J. STARKE
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Patent number: 10423550Abstract: A processing unit connected via a system fabric to multiple processing units calls a first single command in a bus protocol that allows sampling over the system fabric of the capability of snoopers distributed across the processing units to handle an interrupt. The processing unit, in response to detecting at least one first selection of snoopers with capability to handle the interrupt, calling a second single command in the bus protocol to poll the first selection of snoopers over the system fabric for an availability status. The processing unit, in response to detecting at least one second selection of snoopers respond with the available status indicating an availability to handle the interrupt, assigning a single snooper from among the second selection of snoopers to handle the interrupt by calling a third single command in the bus protocol.Type: GrantFiled: October 25, 2017Date of Patent: September 24, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Richard L. Arndt, Florian Auernhammer, Wayne M. Barrett, Robert A. Drehmel, Guy L. Guthrie, Michael S. Siegel, William J. Starke
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Publication number: 20190155771Abstract: A technique for handling interrupts in a data processing system includes receiving, by an interrupt routing controller (IRC), an event routing message (ERM) that includes an event source number for a notification source with an unserviced interrupt. In response to receiving the ERM, the IRC builds an event notification message (ENM) based on the event source number. The IRC determines a scope for the ENM based on an event target group (ETG) associated with the event source number. The IRC issues the ENM to an interrupt presentation controller (IPC) at the scope associated with the ETG.Type: ApplicationFiled: January 22, 2019Publication date: May 23, 2019Inventors: Florian A. Auernhammer, Wayne M. Barrett, Robert A. Drehmel, Michael S. Siegel
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Publication number: 20190121760Abstract: A processing unit connected via a system fabric to multiple processing units calls a first single command in a bus protocol that allows sampling over the system fabric of the capability of snoopers distributed across the processing units to handle an interrupt. The processing unit, in response to detecting at least one first selection of snoopers with capability to handle the interrupt, calling a second single command in the bus protocol to poll the first selection of snoopers over the system fabric for an availability status. The processing unit, in response to detecting at least one second selection of snoopers respond with the available status indicating an availability to handle the interrupt, assigning a single snooper from among the second selection of snoopers to handle the interrupt by calling a third single command in the bus protocol.Type: ApplicationFiled: October 25, 2017Publication date: April 25, 2019Inventors: RICHARD L. ARNDT, FLORIAN AUERNHAMMER, WAYNE M. BARRETT, ROBERT A. DREHMEL, GUY L. GUTHRIE, MICHAEL S. SIEGEL, WILLIAM J. STARKE
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Patent number: 10210112Abstract: A technique for handling interrupts in a data processing system includes receiving, by an interrupt routing controller (IRC), an event routing message (ERM) that includes an event source number for a notification source with an unserviced interrupt. In response to receiving the ERM, the IRC builds an event notification message (ENM) based on the event source number. The IRC determines a scope for the ENM based on an event target group (ETG) associated with the event source number. The IRC issues the ENM to an interrupt presentation controller (IPC) at the scope associated with the ETG.Type: GrantFiled: June 6, 2017Date of Patent: February 19, 2019Assignee: International Business Machines CorporationInventors: Florian A. Auernhammer, Wayne M. Barrett, Robert A. Drehmel, Michael S. Siegel
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Publication number: 20180349305Abstract: A technique for handling interrupts in a data processing system includes receiving, by an interrupt routing controller (IRC), an event routing message (ERM) that includes an event source number for a notification source with an unserviced interrupt. In response to receiving the ERM, the IRC builds an event notification message (ENM) based on the event source number. The IRC determines a scope for the ENM based on an event target group (ETG) associated with the event source number. The IRC issues the ENM to an interrupt presentation controller (IPC) at the scope associated with the ETG.Type: ApplicationFiled: June 6, 2017Publication date: December 6, 2018Inventors: Florian A. Auernhammer, Wayne M. Barrett, Robert A. Drehmel, Michael S. Siegel
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Publication number: 20180349307Abstract: A technique for handling interrupts in a data processing system includes receiving, by an interrupt routing controller (IRC), an event routing message (ERM) that includes an event source number for a notification source with an unserviced interrupt. In response to receiving the ERM, the IRC builds an event notification message (ENM) based on the event source number. The IRC determines a scope for the ENM based on an event target group (ETG) associated with the event source number. The IRC issues the ENM to an interrupt presentation controller (IPC) at the scope associated with the ETG.Type: ApplicationFiled: November 29, 2017Publication date: December 6, 2018Inventors: Florian A. Auernhammer, Wayne M. Barrett, Robert A. Drehmel, Michael S. Siegel
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Patent number: 8069353Abstract: Methods and apparatus for reducing the impact of latency associated with decrypting encrypted data are provided. Rather than wait until an entire packet of encrypted data is validated (e.g., by checking for data transfer errors), the encrypted data may be pipelined to a decryption engine as it is received, thus allowing decryption to begin prior to validation. In some cases, the decryption engine may be notified of data transfer errors detected during the validation process, in order to prevent reporting false security violations.Type: GrantFiled: June 19, 2008Date of Patent: November 29, 2011Assignee: International Business Machines CorporationInventors: Bruce L. Beukema, Robert A. Drehmel, William E. Hall, Jamie R. Kuesel, Gilad Pivonia, Robert A. Shearer
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Publication number: 20080310622Abstract: Methods and devices that may be utilized in systems to dynamically update a security version parameter used to encrypt secure data are provided. The version may be maintained in persistent storage located on a device implementing the encryption, such as a system on a chip (SOC). The persistent storage does not require battery backing and, thus, the cost and complexity associated with conventional systems utilizing battery backed storage may be reduced.Type: ApplicationFiled: March 26, 2008Publication date: December 18, 2008Inventors: ROBERT A. DREHMEL, WILLIAM E. HALL, RUSSELL D. HOOVER
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Patent number: 7461268Abstract: Methods and devices that may be utilized in systems to dynamically update a security version parameter used to encrypt secure data are provided. The version may be maintained in persistent storage located on a device implementing the encryption, such as a system on a chip (SOC). The persistent storage does not require battery backing and, thus, the cost and complexity associated with conventional systems utilizing battery backed storage may be reduced.Type: GrantFiled: July 15, 2004Date of Patent: December 2, 2008Assignee: International Business Machines CorporationInventors: Robert A. Drehmel, William E. Hall, Russell D. Hoover
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Publication number: 20080288780Abstract: Methods and apparatus for reducing the impact of latency associated with decrypting encrypted data are provided. Rather than wait until an entire packet of encrypted data is validated (e.g., by checking for data transfer errors), the encrypted data may be pipelined to a decryption engine as it is received, thus allowing decryption to begin prior to validation. In some cases, the decryption engine may be notified of data transfer errors detected during the validation process, in order to prevent reporting false security violations.Type: ApplicationFiled: June 19, 2008Publication date: November 20, 2008Inventors: BRUCE L. BEUKEMA, Robert A. Drehmel, William E. Hall, Jamie R. Kuesel, Gilad Pivonia, Robert A. Shearer
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Patent number: 7409558Abstract: Methods and apparatus for reducing the impact of latency associated with decrypting encrypted data are provided. Rather than wait until an entire packet of encrypted data is validated (e.g., by checking for data transfer errors), the encrypted data may be pipelined to a decryption engine as it is received, thus allowing decryption to begin prior to validation. In some cases, the decryption engine may be notified of data transfer errors detected during the validation process, in order to prevent reporting false security violations.Type: GrantFiled: September 2, 2004Date of Patent: August 5, 2008Assignee: International Business Machines CorporationInventors: Bruce L. Beukema, Robert A. Drehmel, William E. Hall, Jamie R. Kuesel, Gilad Pivonia, Robert A. Shearer
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Publication number: 20080175381Abstract: Methods and devices that may be utilized in systems to dynamically update a security version parameter used to encrypt secure data are provided. The version may be maintained in persistent storage located on a device implementing the encryption, such as a system on a chip (SOC). The persistent storage does not require battery backing and, thus, the cost and complexity associated with conventional systems utilizing battery backed storage may be reduced.Type: ApplicationFiled: March 27, 2008Publication date: July 24, 2008Inventors: Robert A. Drehmel, William E. Hall, Russell D. Hoover
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Publication number: 20070189313Abstract: A circuit arrangement, method and apparatus utilize communication links that are selectively configurable to operate in both unidirectional and bidirectional modes to communicate data between multiple nodes that are interconnected to one another in a daisy chain configuration. As a result, in many instances communications may be maintained with nodes located both before and after a discontinuity in a daisy chain configuration.Type: ApplicationFiled: April 26, 2007Publication date: August 16, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gerald Bartley, John Borkenhagen, Robert Drehmel, James Marcella
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Publication number: 20060190667Abstract: A circuit and method to provide pipeline bit handling across a bus bridge between two different buses. In a preferred embodiment, the pipeline bit handling circuit provides rule enforcement for a P-bit address modifier across a bus bridge between two different buses with different rules for the P-bit address modifier. In a bus domain where pipeline transactions are allowed if the P-Bit is asserted and are not allowed if the P-Bit is not asserted, embodiments herein allow a master bus device to ensure that all bus devices will see a P=0 command with a defined minimum spacing to any other P=0 command. The required separation for P=0 commands is maintained within the bus bridge. In the preferred embodiments, the separation between P=0 commands is maintained by immediately retrying P=0 commands rather than spacing snoop requests.Type: ApplicationFiled: February 24, 2005Publication date: August 24, 2006Applicant: International Business Machines CorporationInventors: Robert Drehmel, Clarence Ogilvie, Charles Woodruff
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Publication number: 20060190668Abstract: A high speed computer processor system has a high speed interface for a graphics processor. A preferred embodiment combines a PowerPC microprocessor called the Giga-Processor Ultralite (GPUL) 110 from International Business Machines Corporation (IBM) with a high speed interface on a multi-chip module.Type: ApplicationFiled: February 24, 2005Publication date: August 24, 2006Applicant: International Business Machines CorporationInventors: Giora Biran, Matthew Cushing, Robert Drehmel, Allen Gavin, Mark Kautzman, Jamie Kuesel, Ming-I Lin, David Luick, James Marcella, Mark Maxson, Eric Mejdrich, Adam Muff, Clarence Ogilvie, Charles Woodruff
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Publication number: 20060190659Abstract: A bus bridge between a high speed computer processor bus and a high speed output bus. The preferred embodiment is a bus bridge between a GPUL bus for a GPUL PowerPC microprocessor from International Business Machines Corporation (IBM) and an output high speed interface (MPI). Another preferred embodiment is a bus bridge in a bus transceiver on a multi-chip module.Type: ApplicationFiled: February 24, 2005Publication date: August 24, 2006Applicant: International Business Machines CorportionInventors: Giora Biran, Robert Drehmel, Robert Horton, Mark Kautzman, Jamie Kuesel, Ming-i Lin, Eric Mejdrich, Clarence Ogilvie, Charles Woodruff