Abstract: Network elements within a network are configured to retain clock traceability over an asynchronous interface. The network elements can generate and process multi-frames that include two different types of traffic, each synchronized to a different respective clock source. Each of the multi-frames is synchronized to the clock source of one of the traffic types and further includes a timestamp to enable the original clock signal of the other traffic type to be reconstructed at the receiving network element.

Abstract: We disclose an interface device configured to inter-convert CPRI data frames and Optical Transport Units (OTUs). The interface device acquires frame synchronization by temporarily storing data in a buffer bank such that translated sync characters are placed at respective predetermined locations within the buffer bank. Each translated sync character represents, in the corresponding OTU, a respective sync character of a CPRI hyperframe. The interface device is configured to distinguish translated sync characters from payload-data words of identical value based on predetermined alignment, in the buffer bank, of data temporarily stored therein for conversion into the CPRI data format. The interface device advantageously enables multiplexing of a plurality of CPRI links and aggregation and encapsulation of the multiplexed CPRI data into a stream of OTUs for transmission to the intended destination over an Optical Transport Network.

Abstract: Network elements within a network are configured to retain clock traceability over an asynchronous interface. The network elements can generate and process multi-frames that include two different types of traffic, each synchronized to a different respective clock source. Each of the multi-frames is synchronized to the clock source of one of the traffic types and further includes a timestamp to enable the original clock signal of the other traffic type to be reconstructed at the receiving network element.

Abstract: We disclose an interface device configured to inter-convert CPRI data frames and Optical Transport Units (OTUs). The interface device acquires frame synchronization by temporarily storing data in a buffer bank such that translated sync characters are placed at respective predetermined locations within the buffer bank. Each translated sync character represents, in the corresponding OTU, a respective sync character of a CPRI hyperframe. The interface device is configured to distinguish translated sync characters from payload-data words of identical value based on predetermined alignment, in the buffer bank, of data temporarily stored therein for conversion into the CPRI data format. The interface device advantageously enables multiplexing of a plurality of CPRI links and aggregation and encapsulation of the multiplexed CPRI data into a stream of OTUs for transmission to the intended destination over an Optical Transport Network.

Abstract: DSLAMs and associated methods of installing DSLAMs are disclosed where the components of a DSLAM are distributed in a DSL network. A distributed DSLAM as provided herein includes digital signal processing components implemented in a centralized system (e.g., a central office) on the DSL network. The distributed DSLAM also includes digital/analog conversion components (e.g., analog front end (AFE) components) implemented in a distributed node on the DSL network that is remote from the centralized system. The distributed DSLAM also includes a spanned communication link (e.g., optical fiber) between the digital signal processing components and the digital/analog conversion components. The digital signal processing components in the centralized system are considered more likely to be upgraded than the digital/analog conversion components in the distributed node. Thus, upgrades for the DSLAM can frequently be performed at the centralized system instead of at the distributed node.

Abstract: A novel backplane routing and configuration (200) supports a full mesh architecture. In this novel configuration, a circuit pack determines which backplane signals to use for a transmission based on the relative distance across the backplane between the board sending the communication and the board receiving the communication. Boards sending the same relative distance use the same rows of signals (204). That is, each row associated with the meshed interconnection is assigned a relative shift or distance for a connection. The rows (204) that represent a greater relative distance for shift between boards are intermixed next to rows (204) that have a relatively short distance between shifts or boards. In this manner, the number of layers required is minimized and the utilization of routing channels is optimized. In particular, for a N slot backplane with one routing channel between rows, (N/2+1) layers are required, rather than N layers. And, vertical routing is not required.

Abstract: A method and apparatus for encoding and decoding m-bit groups of digital data, where m is at least eight, into serial n bit groups such that each encoded serial n-bit group has sufficient data transitions therein to maintain the synchronization of a phase locked loop clock recovery circuit in a high speed serial link of a communication path. Further, this method and apparatus provides a duty cycle that is within an operational range of the ideal 50 percent, which reduces voltage drift of a.c. coupled high speed serial data links, or reduces thermal drift of optically coupled high speed serial data links.

Abstract: The present invention provides a high impedance optical receiver circuit for use in integrated circuits. The receiver circuit consists of an optical detecting device connected to the gate of an FET device and further connected to a diode providing a load impedance. The FET device is connected to a biasing voltage through a biasing resistive element and to a conditioning stage output. The use of a diode to provide a load impedance allows for a smaller and easier to manufacture receiver circuit than would be possible using either a load resistor or a load FET. According to one aspect of the present invention, a digital integrated circuit employing SEED technology incorporates a plurality of diode-loaded receiver in an array of optical receiver circuits to reduce the footprint of the overall SEED circuit array.

Abstract: A fiber optical array with precision fiber and positioning and a process for manufacturing such an array. The position of the ends of the optical fibers depends upon placement within a target that has been lithographed using highly precise lithography similar to that used in VLSI integrated circuits. The placement of an end with its core within its target is performed with the aid of microscopes and micro-manipulators. Once an end is in the proper location, ultraviolet curable adhesive is used to permanently fix its position precisely. Arrays having positional precision to within 1 micrometer are achievable by this invention.