Abstract: A memory cell includes: a charge storage element (e.g., capacitor); a switch constructed and arranged to selectively connect the charge storage element to a first data line, responsive to a first select signal; and a gain element having an input connected to receive a signal from the capacitor and constructed and arranged to selectively provide a corresponding output signal to a second data line, responsive to a second select signal. The switch can be a FET having a drain connected to the first data line, a source connected to the capacitor and a gate connected to the first select signal. The gain element can be a FET having a gate connected to the capacitor, a source connected to the second data line and a drain selectively connected to one of an upper power supply and a lower power supply. The switch can transfer a signal from the first data line onto the capacitor and can transfer a signal from the capacitor onto the first data line when selected by the first select signal.

Abstract: Various aspects of an integrated circuit having a DRAM are disclosed. In one embodiment an integrated circuit includes a DRAM that (1) pre-charges the bit lines to a voltage that is biased toward a weaker one of two memory cell logic states, (2) selectively stores data in an inverted form that reduces the power needed to refresh such data (in at least one embodiment), (3) retains data in the sense/latch circuits and use such circuits as a form of cache to reduce the frequency that memory cells are accessed and thereby reduce memory access time, and (4) supplies a reference (e.g., VPP) from a circuit that employs an alternate, lower power, operating mode (e.g., if the DRAM is in standby).

Abstract: Various aspects of an integrated circuit having a DRAM are disclosed. In one embodiment an integrated circuit includes a DRAM that (1) pre-charges the bit lines to a voltage that is biased toward a weaker one of two memory cell logic states, (2) selectively stores data in an inverted form that reduces the power needed to refresh such data (in at least one embodiment), (3) retains data in the sense/latch circuits and use such circuits as a form of cache to reduce the frequency that memory cells are accessed and thereby reduce memory access time, and (4) supplies a reference (e.g., VPP) from a circuit that employs an alternate, lower power, operating mode (e.g., if the DRAM is in standby).

Abstract: An integrated circuit assembly is formed with an integral power supply decoupling capacitor for monolithic circuitry in a semiconductor substrate by using the substrate itself as one plate of the capacitor. A dielectric is formed on the "back" side, or surface, of the substrate (i.e., the surface opposite the surface in which component structures are formed) such as by growing a native oxide thereon. Using a conductive epoxy, the back side of the substrate (actually, the dielectric layer thereon) is then attached to a conductive foundation member, which forms the other plate of the capacitor when a potential is applied across the substrate and the foundation member. The conductive foundation member also may be connected to a heat sink structure integral with the package. The heat sink may extend through a window in the package, providing a path and surface via which heat may be transferred to an external heat sink if a larger heat sink mass is needed.

Abstract: A sense amplifier for determining the state of a memory cell of a random access memory includes first and second transistors connected in a differential amplifier configuration. The first and second transistors have control electrodes coupled to Bit and Bit B lines, respectively, for sensing a state of the memory cell. The sense amplifier further includes third and fourth transistors connected in a differential amplifier configuration. The differential amplifier configuration has an offset error and provides differential outputs for indicating the state of the memory cell during a read phase. The sense amplifier further includes first and second capacitors respectively coupled between the control electrodes of the third and fourth transistors and a reference potential, and a feedback circuit for coupling voltages representative of the offset error to the first and second capacitors during a nulling phase in which the Bit and Bit B lines are not being read.

Abstract: In a dynamic MOS memory, e.g. a RAM, the charge on the capacitor of a reference cell is restored following a read or refresh operation by coupling a reference voltage generator to the RAM bit line. The generator produces the reference voltage at the output of a buffer whose input is coupled to two capacitors after these have been charged to different voltages and their charges shared. The arrangement allows for transistor thresholds without requiring bootstrapping, is insensitive to manufacturing process variations in that all of the capacitors can be similar, provides for enhanced operation speed, and provides for qualitative signal margin analysis.