Abstract: An I/O communication adapter receives from a processor core an I/O command referencing an effective address within an effective address space of the processor core that identifies a storage location. In response to receipt of the I/O command, the I/O communication adapter translates the effective address into a real address by reference to a translation data structure. The I/O communication adapter then accesses the storage location utilizing the real address to perform an I/O data transfer specified by the I/O command.

Abstract: A data processing system includes an instruction pipeline, including one or more execution units that execute instructions and an instruction sequencing unit that dispatches instructions to the execution units for execution. The data processing system further includes a memory controller for a memory containing an instruction trace log and an interconnect coupled to the instruction pipeline and to the memory controller. The interconnect transmits to the memory controller for storage in the instruction trace log instructions processed within the instruction pipeline.

Abstract: A processing unit includes a processor core, an input/output (I/O) communication adapter coupled to the processor core, and a cache system coupled to the processor core and to the I/O communication adapter. The cache system including a cache array, a cache directory and a cache controller. The cache controller snoops I/O communication by the I/O communication adapter and, in response to snooping the I/O communication adapter performing an I/O data write of outgoing data in an exclusive state, invalidates corresponding data stored within the cache array.

Abstract: An integrated circuit, such as a processing unit, includes a substrate and integrated circuitry formed in the substrate. The integrated circuitry includes a processor core that executes instructions, an interconnect interface, coupled to the processor core, that supports communication between the processor core and a system interconnect external to the integrated circuit, and at least a portion of an external communication adapter, coupled to the processor core, that supports input/output communication via an input/output communication link.

Abstract: A processor communication register (PCR) contained in each processor within a multiprocessor system provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel multi-processing. Each processor has exclusive rights to store to a sector within each PCR and has continuous access to read the contents of its own PCR. Each processor updates its exclusive sector within all of the PCRs, instantly allowing all of the other processors to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the multiprocessor system by providing processor communications to be immediately transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.

Abstract: A processor communication register (PCR) contained in each processor within a multiprocessor cluster network provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel multi-processing. Each processor has exclusive rights to store to a sector within each PCR within the cluster network and has continuous access to read the contents of its own PCR. Each processor updates its exclusive sector within all of the PCRs via a private protocol or dedicated wireless network, instantly allowing all of the other processors within the cluster network to see the change within the PCR data, and bypassing the cache subsystem.

Abstract: Processor communication registers (PCRs) contained in each processor within a multiprocessor system and interconnected by a specialized bus provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel multi-processing. Each processor has exclusive rights to store to a sector within each PCR and has continuous access to read the contents of its own PCR. Each processor updates its exclusive sector within all of the PCRs utilizing communication over the specialized bus, instantly allowing all of the other processors to see the change within the PCR data, and bypassing the cache subsystem.

Abstract: A processor communication register (PCR) contained within a multiprocessor cluster system provides enhanced processor communication. The PCR stores information that is useful in pipelined or parallel multi-processing. Each processor cluster has exclusive rights to store to a sector within the PCR and has continuous access to read its contents. Each processor cluster updates its exclusive sector within the PCR, instantly allowing all of the other processors within the cluster network to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the processor cluster network by providing processor communications to be immediately networked and transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.

Abstract: A method and system are disclosed for predicting, based on historical information, a second level interrupt handler (SLIH) to service an interrupt. The predicted SLIH is speculatively executed concurrently with a first level interrupt handler (FLIH), which determines the correct SLIH for the interrupt. If the predicted SLIH has been correctly predicted, execution of the SLIH called by the FLIH is discontinued, and the predicted SLIH completes execution. If the predicted SLIH is mispredicted, then the execution of the predicted SLIH is discontinued, and the SLIH called by the FLIH continues to completion.

Abstract: A method and system are disclosed for managing saved process states in a memory of a data processing system that has multiple partitions executing independent operating systems. A hypervisor manager affords access to any processor in the data processing system for the purpose of storing process states for that processor to the memory, independent of the operating system running on the processor.

Abstract: A method and system are disclosed for managing a hard architected state of a processor that is critical for executing a process in the processor. A shadow copy of the hard architected state is stored from the processor to memory when an interrupt is received by the processor. The shadow copy of the hard architected permits rapid saving of the hard architected state for the interrupted process, so that the architected state of a next process can be immediately stored in the processor.

Abstract: A method and system are disclosed for running a manufacturing-level test program on an installed processor by interrupting processor execution of a non-test process. Periodic execution of the manufacturing-level test program allows the processor to continually self-test during normal function operation, in order to facilitate proper maintenance and function of the processor and a data processing system of which the processor is a part.

Abstract: A method and system are disclosed for pre-loading a hard architected state of a next process from a pool of idle processes awaiting execution. When an executing process is interrupted on the processor, a hard architected state, which has been pre-stored in the processor, of a next process is loaded into architected storage locations in the processor. The next process to be executed, and thus its corresponding hard architected state that is pre-stored in the processor, are determined based on priorities assigned to the waiting processes.

Abstract: A method and system are disclosed for managing stored soft state information, such as the contents of cache memory and address translation information that are non-critical for executing a process within a processor. The soft states of idle processes are stored in system memory in virtual caches. Cache coherency of the soft states is maintained by snooping kill-type operations against the virtual caches in system memory.

Abstract: A method and system are disclosed for saving soft state information, which is non-critical for executing a process in a processor, upon a receipt of a process interrupt by the processor. The soft state is transmitted to a memory associated with the processor via a memory interface. Preferably, the soft state is transmitted within the processor to the memory interface via a scan-chain pathway within the processor, which allows functional data pathways to remain unobstructed by the storage of the soft state. Thereafter, the stored soft state can be restored from memory when the process is again executed.

Abstract: A method of storing values in a sliced cache by providing separate, but coordinated, reservation units for each cache slice. When a load-with-reserve (larx) operation is issued from the processor core as part of an atomic read-modify-write sequence, a message is broadcast to each of the cache slices to clear reservation flags in the slices; a reservation flag is also set in the target cache slice, and a memory address associated with the load-with-reserve operation is loaded into a reservation unit of the target cache slice. When a conditional store operation is issued from the core to complete the atomic read-modify-write sequence, a second message is broadcast to any non-target cache slice of the processing unit to clear reservation flags in the non-target cache slice(s).

Abstract: An information handling system includes a producer that outputs packets, a buffer that receives packets from the producer, buffers the packets, and eventually outputs the packets, and a control unit that controls the flow of packets from the producer to the buffer. The control unit receives as inputs a producer output indication indicating that the producer has output a packet to the buffer and a buffer output indication indicating that the buffer has output a packet. Based upon a capacity of the buffer, a number of the producer output indications, a number of buffer output indications, and a number of grant messages output to the producer within a feedback latency of the control unit, the control unit whether the producer can output a packet without packet loss. In response to a determination that the producer can output a packet without packet loss, the control unit outputs a grant message to the producer indicating that the producer is permitted to output a packet.

Abstract: An information handling system includes a plurality of producers that output packets of information, at least one consumer of the packets, and an information pipeline coupling the consumer and at least a particular producer among the plurality of producers. The information pipeline includes a shared resource having a bandwidth shared by multiple of the plurality of producers. The information handling system further includes a control unit that regulates packet output of the particular producer and that receives as inputs a producer output indication indicating that the particular producer output a packet and a shared resource input indication indicating that a packet output by the particular producer has been accepted by the shared resource for transmission to the consumer.

Abstract: An information handling system includes a producer that outputs packets of information, a plurality of buffers that can each receive packets from the producer and output the packets, and a control unit. The control unit receives at least one producer output indication indicating whether the producer output a packet to one of the plurality of buffers and a plurality of buffer output indications that each indicate whether a respective one of the plurality of buffers has output a packet. Based upon capacities of the plurality of buffers, the producer output indications, the buffer output indications and a number of grant messages output to the producer within a feedback latency of the control unit, the control unit whether the producer can output a packet without packet loss. If so, the control unit provides a grant message to the producer indicating that the producer is permitted to output a packet.

Abstract: An information handling system includes a plurality of sequentially connected units including a first unit, a second unit and a third unit. Packets of information flow from the first unit directly to the second unit and then to the third unit, and each of the plurality of units provides a respective dynamic output indication indicating if that unit output a packet. The information handling system further includes a control unit that determines, utilizing all of the plurality of dynamic output indications, packet buffering capacities of the plurality of units, and guaranteed packet flows between adjacent ones of the plurality of units, if the first unit can output a packet directly to the second unit without packet loss. In response to this determination, the control unit outputs a control signal to the first unit.