Patents by Inventor Robert Allen Drehmel
Robert Allen Drehmel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7873773Abstract: A circuit arrangement, method and apparatus utilize communication links that are selectively configurable to operate in both unidirectional and bidirectional modes to communicate data between multiple nodes that are interconnected to one another in a daisy chain configuration. As a result, in many instances communications may be maintained with nodes located both before and after a discontinuity in a daisy chain configuration.Type: GrantFiled: April 26, 2007Date of Patent: January 18, 2011Assignee: International Business Machines CorporationInventors: Gerald Keith Bartley, John Michael Borkenhagen, Robert Allen Drehmel, James Anthony Marcella
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Patent number: 7757032Abstract: A bus bridge between a high speed computer processor bus and a high speed output bus. The preferred embodiment is a bus bridge between a GPUL bus for a GPUL PowerPC microprocessor from International Business Machines Corporation (IBM) and an output high speed interface (MPI). Another preferred embodiment is a bus bridge in a bus transceiver on a multi-chip module.Type: GrantFiled: August 20, 2008Date of Patent: July 13, 2010Assignee: International Business Machines CorporationInventors: Giora Biran, Robert Allen Drehmel, Robert Spencer Horton, Mark E. Kautzman, Jamie Randall Kuesel, Ming-i Mark Lin, Eric Oliver Mejdrich, Clarence Rosser Ogilvie, Charles S. Woodruff
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Patent number: 7469312Abstract: A method for bridging between a high speed computer processor bus and a high speed output bus. The preferred embodiment is a method for bridging between a GPUL bus for a GPUL PowerPC microprocessor from International Business Machines Corporation (IBM) and an output high speed interface (MPI).Type: GrantFiled: February 24, 2005Date of Patent: December 23, 2008Assignee: International Business Machines CorporationInventors: Giora Biran, Robert Allen Drehmel, Robert Spencer Horton, Mark E. Kautzman, Jamie Randall Kuesel, Ming-i Mark Lin, Eric Oliver Mejdrich, Clarence Rosser Ogilvie, Charles S. Woodruff
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Publication number: 20080307147Abstract: A bus bridge between a high speed computer processor bus and a high speed output bus. The preferred embodiment is a bus bridge between a GPUL bus for a GPUL PowerPC microprocessor from International Business Machines Corporation (IBM) and an output high speed interface (MPI). Another preferred embodiment is a bus bridge in a bus transceiver on a multi-chip module.Type: ApplicationFiled: August 20, 2008Publication date: December 11, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Giora Biran, Robert Allen Drehmel, Robert Spencer Horton, Mark E. Kautzman, Jamie Randall Kuesel, Ming-i Mark Lin, Eric Oliver Mejdrich, Clarence Rosser Ogilvie, Charles S. Woodruff
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Patent number: 7275125Abstract: A circuit and method to provide pipeline bit handling across a bus bridge between two different buses. In a preferred embodiment, the pipeline bit handling circuit provides rule enforcement for a P-bit address modifier across a bus bridge between two different buses with different rules for the P-bit address modifier. In a bus domain where pipeline transactions are allowed if the P-Bit is asserted and are not allowed if the P-Bit is not asserted, embodiments herein allow a master bus device to ensure that all bus devices will see a P=0 command with a defined minimum spacing to any other P=0 command. The required separation for P=0 commands is maintained within the bus bridge. In the preferred embodiments, the separation between P=0 commands is maintained by immediately retrying P=0 commands rather than spacing snoop requests.Type: GrantFiled: February 24, 2005Date of Patent: September 25, 2007Assignee: International Business Machines CorporationInventors: Robert Allen Drehmel, Clarence Rosser Ogilvie, Charles S. Woodruff
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Patent number: 7254663Abstract: A circuit arrangement, method and apparatus utilize communication links that are selectively configurable to operate in both unidirectional and bidirectional modes to communicate data between multiple nodes that are interconnected to one another in a daisy chain configuration. As a result, in many instances communications may be maintained with nodes located both before and after a discontinuity in a daisy chain configuration.Type: GrantFiled: July 22, 2004Date of Patent: August 7, 2007Assignee: International Business Machines CorporationInventors: Gerald Keith Bartley, John Michael Borkenhagen, Robert Allen Drehmel, James Anthony Marcella
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Patent number: 7234017Abstract: A high speed computer processor system has a high speed interface for a graphics processor. A preferred embodiment combines a PowerPC microprocessor called the Giga-Processor Ultralite (GPUL) 110 from International Business Machines Corporation (IBM) with a high speed interface on a multi-chip module.Type: GrantFiled: February 24, 2005Date of Patent: June 19, 2007Assignee: International Business Machines CorporationInventors: Giora Biran, Matthew Adam Cushing, Robert Allen Drehmel, Allen James Gavin, Mark E. Kautzman, Jamie Randall Kuesel, Ming-I Mark Lin, David Arnold Luick, James Anthony Marcella, Mark Owen Maxson, Eric Oliver Mejdrich, Adam James Muff, Clarence Rosser Ogilvie, Charles S. Woodruff
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Patent number: 6895482Abstract: An improved computer memory subsystem determines the most efficient memory command to execute. The physical location and any address dependency of each incoming memory command to a memory controller is ascertained and that information accompanies the command for categorization into types of command. For each type of memory command, there exists a command FIFO and associated logic in which a programmable number of the memory commands are selected for comparison with each other, with the memory command currently executing, and with the memory command previously chosen for execution. The memory command having the least memory cycle performance penalty is selected for execution unless that memory command has an address dependency. If more than one memory command of that type has the least memory cycle performance penalty, then the oldest is selected for execution.Type: GrantFiled: September 10, 1999Date of Patent: May 17, 2005Assignee: International Business Machines CorporationInventors: Herman Lee Blackmon, Robert Allen Drehmel, Kent Harold Haselhorst, James Anthony Marcella
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Patent number: 6836831Abstract: Methods and apparatus in a computer system are disclosed for providing a memory controller featuring a dedicated bank sequencer for each memory bank in a memory system. Each bank sequencer controls the dispatch of load and store requests to a central controller such that each request sent to the central controller can be served by the associated memory bank at the time that the central controller receives the request. Since every request received by the central controller is valid from a bank timing standpoint, the central controller is free to process the requests from a predetermined priority basis, without concern for bank availability. This significantly improves the design of the memory controller in the processing system.Type: GrantFiled: August 8, 2002Date of Patent: December 28, 2004Assignee: International Business Machines CorporationInventors: John Michael Borkenhagen, Robert Allen Drehmel, Brian T. Vanderpool
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Publication number: 20040030849Abstract: Methods and apparatus in a computer system are disclosed for providing a memory controller featuring a dedicated bank sequencer for each memory bank in a memory system. Each bank sequencer controls the dispatch of load and store requests to a central controller such that each request sent to the central controller can be served by the associated memory bank at the time that the central controller receives the request. Since every request received by the central controller is valid from a bank timing standpoint, the central controller is free to process the requests from a predetermined priority basis, without concern for bank availability. This significantly improves the design of the memory controller in the processing system.Type: ApplicationFiled: August 8, 2002Publication date: February 12, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John Michael Borkenhagen, Robert Allen Drehmel, Brian T. Vanderpool
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Patent number: 6684279Abstract: A method, apparatus, and computer program product are described for controlling data transfer. A next data packet to be transferred is retrieved. A determination is made regarding whether a data bus busy signal is asserted. If the data bus busy signal is asserted, a determination is made regarding whether a data bus grant signal is asserted. If the data bus grant signal is asserted, the next data packet is transferred on the next cycle after a last cycle of data transfer of a previous data packet.Type: GrantFiled: November 8, 1999Date of Patent: January 27, 2004Assignee: International Business Machines CorporationInventors: Robert Earl Kruse, Robert Allen Drehmel
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Patent number: 6628662Abstract: A method and system for arbitrating data transfers between devices connected via electronically isolated buses at a switch. In accordance with the method and system of the present invention, multiple arbitration controllers are interposed between devices and a switch to which the devices are connected, wherein each of the multiple arbitration controllers are effective to select a data transfer operation and detect collisions between said selected data transfer operations. The switch is enabled for any selected data transfer operations between which collisions are not detected. The switch is also enabled for only one of the selected data transfer operations between which collisions are detected. Any selected data transfer operations for which the switch is not enabled are deferred.Type: GrantFiled: November 29, 1999Date of Patent: September 30, 2003Assignee: International Business Machines CorporationInventors: Herman Lee Blackmon, Robert Allen Drehmel, Kent Harold Haselhorst, James Anthony Marcella
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Patent number: 6557069Abstract: An internal processor/memory bus contains an address portion for transmitting addresses and commands, having a series of hierarchical uni-directional links between processors and local repeaters (ARPs), and between the ARPs and a central repeater (ASW). A command propagates from a requesting device to its local ARP, to the ASW. From the ASW, the command is broadcast to all devices on the bus by transmitting to all ARPs or directly attached memory, and from the ARPs to the devices. Preferably, the ASW globally arbitrates the address bus, and all commands propagate at pre-defined clock cycles through the bus. Preferably, each device on the bus independently signals a response via a separate response link running directly to a global collector, which collects all responses and broadcasts a single system-wide response back to the devices.Type: GrantFiled: November 12, 1999Date of Patent: April 29, 2003Assignee: International Business Machines CorporationInventors: Robert Allen Drehmel, Kent Harold Haselhorst, Russell Dean Hoover, James Anthony Marcella, George Wayne Nation
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Patent number: 6526469Abstract: A processor-memory bus comprises a command portion for transmitting addresses and commands, having a unidirectional input portion for transmitting commands to a central repeater unit, and a unidirectional broadcast portion for broadcasting commands from the repeater. The input portion comprises a plurality of links running from different devices, wherein each link is less than the full width of the broadcast bus portion. A command is transmitted over the input portion in a plurality of bus cycles, and broadcast over the broadcast portion in a single bus cycle. Since multiple input links connect to the central command repeater, it is possible to keep the broadcast bus full notwithstanding the fact that multiple bus cycles are required to transmit an individual command on the input portion. Preferably, the links are arranged hierarchically, from processors to local repeaters, from local repeaters to the central repeater, and back again.Type: GrantFiled: November 12, 1999Date of Patent: February 25, 2003Assignee: International Business Machines CorporationInventors: Robert Allen Drehmel, Kent Harold Haselhorst, Russell Dean Hoover, James Anthony Marcella
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Patent number: 6523080Abstract: A shared bus non-sequential data ordering method and apparatus are provided. A maximum bus width value and a minimum transfer value are identified. A minimum number of sub-transfers is identified responsive to the identified maximum bus width value and the minimum transfer value. A bus unit having a maximum number of chips to receive and/or send data receives data in a predefined order during multiple sub-transfers. During each data sub-transfer, a corresponding predefined word is transferred to each chip of the bus unit.Type: GrantFiled: January 27, 1998Date of Patent: February 18, 2003Assignee: International Business Machines CorporationInventors: Herman Lee Blackmon, Robert Allen Drehmel, Lyle Edwin Grosbach, Kent Harold Haselhorst, David John Krolak, James Anthony Marcella, Peder James Paulson
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Patent number: 6513091Abstract: A method and apparatus for routing data between bus devices, where each bus device is connected to a centralized switch via a point-to-point bus connection. The plurality of point-to-point bus connections collectively form a system bus. After a command is issued on the system bus, each bus device responds to the issued command by transmitting an address status response to a response combining logic module. The response combining logic module identifies which of the bus devices responded with a positive acknowledgment to the issued command, then forwards a device identifier of the bus device responding with the positive acknowledgment to the switch. The switch uses the device identifier returned via the response combining logic to route the data transfer associated with the issued command.Type: GrantFiled: November 12, 1999Date of Patent: January 28, 2003Assignee: International Business Machines CorporationInventors: Herman Lee Blackmon, Robert Allen Drehmel, Kent Harold Haselhorst, James Anthony Marcella
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Patent number: 6505306Abstract: An apparatus, program product and method initialize a redundant memory device by delaying the switchover of non-initialization fetch operations from a failed memory device to the redundant memory device until after initialization of the redundant memory device is complete. Consequently, during initialization, the non-initialization fetch operations are directed to the failed memory device, while non-initialization store operations are directed to the redundant device.Type: GrantFiled: September 15, 1999Date of Patent: January 7, 2003Assignee: International Business Machines CorporationInventors: Herman Lee Blackmon, Robert Allen Drehmel, Kent Harold Haselhorst, James Anthony Marcella
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Patent number: 6295591Abstract: A method of providing maintenance for a memory device of a computer system without interrupting operation of the computer system, by partially mirroring a primary memory array in a secondary memory array, wherein the secondary memory array has a different amount of available memory than the primary memory array. Values are copied from the primary memory array to the permanent storage device, allowing the primary memory array to quiesce and be serviced while using the secondary memory array to operate the computer system. Thereafter, the primary memory array is brought on-line, and the mirrored values are written back from the secondary memory array to the primary memory array. The memory service program itself may be embedded in the operating system. In an illustrative embodiment, the primary memory array is located on a first removable memory card, and the secondary memory array is located on a second removable memory card. The amount of memory available in the secondary memory array may be programmable.Type: GrantFiled: March 30, 1999Date of Patent: September 25, 2001Assignee: International Business Machines CorporationInventors: Richard Bealkowski, Scott Douglas Clark, Sudhir Dhawan, Robert Allen Drehmel
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Patent number: 6247100Abstract: A method and system for transmitting address commands in a multiprocessor system comprising multiple nodes interconnected by an address bus. A request for arbitration of an address bus is transmitted from a controller within a node of multiple nodes to an arbitration switch, which controls transmission across the address bus. The address command is transmitted from the controller to the arbitration switch, in response to receiving a grant of arbitration of the address bus. The address command is then broadcast from the arbitration switch to a controller within each node of multiple nodes, in response to receiving the address command at the arbitration switch. The address command is broadcast from the controller within each node, in response to receiving the broadcast address command at the controller within each node, such that all address command transmissions on the address bus are transmitted to each processor within a multiprocessor system.Type: GrantFiled: January 7, 2000Date of Patent: June 12, 2001Assignee: International Business Machines CorporationInventors: Robert Allen Drehmel, Kent Harold Haselhorst, Russell Dean Hoover, James Anthony Marcella
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Patent number: RE44342Abstract: A processor-memory bus comprises a command portion for transmitting addresses and commands, having a unidirectional input portion for transmitting commands to a central repeater unit, and a unidirectional broadcast portion for broadcasting commands from the repeater. The input portion comprises a plurality of links running from different devices, wherein each link is less than the full width of the broadcast bus portion. A command is transmitted over the input portion in a plurality of bus cycles, and broadcast over the broadcast portion in a single bus cycle. Since multiple input links connect to the central command repeater, it is possible to keep the broadcast bus full notwithstanding the fact that multiple bus cycles are required to transmit an individual command on the input portion. Preferably, the links are arranged hierarchically, from processors to local repeaters, from local repeaters to the central repeater, and back again.Type: GrantFiled: August 15, 2005Date of Patent: July 2, 2013Assignee: International Business Machine CorporationInventors: Robert Allen Drehmel, Kent Harold Haselhorst, Russel Dean Hoover, James Anthony Marcella