Abstract: A multiprocessor computer system comprises a first node operable to access memory local to a remote node by receiving a virtual memory address from a requesting entity in node logic in the first node. The first node creates a network address from the virtual address received in the node logic, where the network address is in a larger address space than the virtual memory address, and sends a fast memory access request from the first node to a network node identified in the network address.

Abstract: A processor core, comprises one or more vector units operable to change between a fine-grained vector mode having a shorter maximum vector length and a coarse-grained vector mode having a longer maximum vector length. Changing vector modes comprises halting all instruction stream execution in the core, flushing one or more registers in a register space, reconfiguring one or more vector registers in the register space, and restarting instruction execution in the core.

Abstract: A multiprocessor computer system has a plurality of first processors having a first addressable memory space, and a plurality of second processors having a second addressable memory space. The second addressable memory space is of a different size than the first addressable memory space, and the first addressable memory space and second addressable memory space comprise a part of the same common address space.

Abstract: A multiprocessor computer system comprises a sending processor node and a receiving processor node. The sending processor node is operable to send packets comprising part of a message to a receiver, to maintain a message buffer entry in the sender comprising the sent packets, to track acknowledgment from the receiver that sent packets have been received; to maintain a timer indicating the time since message data has been sent, and to resend packets not acknowledged upon the timer reaching a timeout state. The receiving processor node is operable to send acknowledgement to the sender that received packets have been received, to track packets using a received message table to track which packets comprising part of the message have been received and whether all packets in the message have been received, and to process packets once all packets in a message are received to reassemble the received message.

Abstract: A multiprocessor computer system comprises a sending processor node and a receiving processor node. The sending processor node is operable to send packets comprising part of a message to a receiver, and to send a message complete packet after all packets in the message are sent. The message complete packet includes an indicator of the number of packets in the message, and the message is recognized as complete in the receiver once the number of packets indicated in the message complete packet have been received for the message. The sender tracks acknowledgment from the receiver of receipt of the sent packets; and notifies the receiver when it has received all packets comprising a part of the message.

Abstract: A system and method for routing a packet between ports for use in a router having a plurality of ports, including a first and a second port, wherein each port includes a plurality of look-up tables (LUTs) and a look-up table select connected to the LUTs. Routing information is loaded into each of the plurality of LUTs while LUT selection information is loaded in the look-up table select. A packet having a plurality of destination bits is received at the first port and a destination port selected within the router to receive the packet. The destination port is selected by applying two or more of the destination bits to the plurality of LUTs in the first port and selecting an output of the plurality of LUTs as a function of one or more of the destination bits, wherein the selected output indicates the port selected to receive the packet. The packet is then routed to the output of the selected port.