Abstract: A circuit is disclosed which adjusts the phase of a signal within an LC sinusoidal or a ring or other capacitive oscillator. The circuit uses FETs as capacitors. The gates of the FETs are connected to the capacitive node of the oscillator. The variable voltage source changes the state of the FET from depleted to inverted mode or from inverted to depleted mode which in turn dramatically changes the capacitance of the FET. The change of state exists for only a few clock cycles, typically less than five cycles, so that only the capacitance within the oscillator is instantaneously affected which changes adds as incremental/decremental frequency to adjust only the phase of the oscillation frequency. In this fashion, the average oscillation frequency not affected.

Abstract: A circuit is disclosed which uses less power and is responsive to high frequencies which can detect if a signal has sufficient amplitude. The signal of interest is input to an active semiconductor device. The other inputs to the active device are set by the value of the amplitude which the signal must be less than/greater than. The circuit is especially useful in an oscillator which generates high frequency clock signals to determine if the clock signals have sufficient amplitude to drive the electronics.

Abstract: A circuit arrangement for correcting magneto-resistive head asymmetry includes a shift circuit which receives a read signal from a magneto-resistive head, and a polarity signal indicative of the polarity of any asymmetry of the read signal. Depending on the polarity of the asymmetry, the shift circuit either adds or subtracts a shift voltage to the read signal to produce a shifted read signal. The shift circuit outputs the read signal, the shifted read signal, and the shift voltage. First, second and third gain circuits are provided, which receive the read signal, the shifted read signal, and the shift voltage, respectively, and which each receive a respective control signal. The first, second and third gain circuits provide respective outputs amplified proportionally based on the respective control signals. Control circuitry provides the polarity signal to the shift circuit and the respective control signals to the first, second and third gain circuits, based on an amount of correction required.

Abstract: A method and circuits are provided for high speed powerup of an analog reference source, such as used in a direct access storage device (DASD). The high speed powerup circuits for the analog reference source include a biasing current source. Biasing circuitry is provided for establishing a first bias reference voltage level. An enable input is provided for disabling and for enabling powerup of the analog reference source. A transistor switch is coupled between the bias reference voltage level and the analog reference source. The transistor switch is operatively controlled by the enable input for driving the analog reference source and enabling fast powerup of the analog reference source.

Abstract: An interleaved finite impulse response (FIR) filter apparatus is provided for data detection in a direct access storage device. The FIR filter includes a plurality of sample and hold circuits. Each sample and hold circuit samples an input signal sequentially at a clock rate. At least one set of multiple multipliers is coupled to the plurality of sample and hold circuits. Each multiplier multiplies a sample by a predefined value and provides a multiplier product at the clock rate. At least a pair of summing functions are coupled to the set of multipliers. Each summing function adds a predetermined combination of respective multiplier products and provides at least a pair of interleave outputs. Each of the interleave outputs is provided at less than the clock rate.

Abstract: A method for detecting servo data and an interleaved dibit detection apparatus are provided for servo data detection in a direct access storage device. The interleaved dibit detection apparatus includes a new dibit threshold detector for detecting a predefined threshold level of a new interleave servo signal and providing a new detected dibit output. An old dibit threshold detector detects the predefined threshold level of an old interleave servo signal and provides an old detected dibit output. A combining function coupled to the new dibit threshold detector and the old dibit threshold detector provides a combined detected dibit output.

Abstract: A high speed differential analog to digital converter (ADC) is provided. The high speed differential ADC includes a driver section, a comparator section and a decoder section. The driver section includes a pair of series connected resistor ladders. A positive phase and negative phase emitter follower transistor pair is connected to the pair of series connected resistor ladders. The positive phase and negative phase emitter follower transistor has a collector connected to a supply voltage and has an emitter coupled to a respective one of the pair of series connected resistor ladders. A respective positive phase and negative phase AC current source drives the base of the respective positive phase and negative phase emitter follower transistor. A reference DC current source is coupled to the base of the positive phase and negative phase emitter follower transistors for determining a range of the ADC. A current source transistor pair biases the emitter follower transistor pair.

Abstract: High-performance bipolar transistors with improved wiring options and fabrication methods therefore are set forth. The bipolar transistor includes a base contact structure that has multiple contact pads which permit multiple device layouts when wiring to the transistor. For example, a first device layout may comprise a collector-base-emitter device layout, while a second device layout may comprise a collector-emitter-base device layout. More specifically, the base contact structure at least partially surrounds the emitter and has integral contact pads which extend away from the emitter. Further, sections of the base contact structure are disposed on an insulating layer outside of the perimeter of the base region of the transistor, while other sections directly contact the base region. Specific details of the bipolar transistor, and fabrication methods therefore are also set forth.