Patents by Inventor Robert B. Clark-Phelps

Robert B. Clark-Phelps has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7071051
    Abstract: According to one exemplary embodiment, a method for forming a field-effect transistor on a substrate comprises a step of forming a buffer layer on the substrate, where the buffer layer comprises ALD silicon dioxide. The buffer layer can be formed by utilizing a silicon tetrachloride precursor in an atomic layer deposition process, for example. The buffer layer comprises substantially no pin-hole defects and may have a thickness, for example, that is less than approximately 5.0 Angstroms. The method further comprises forming a high-k dielectric layer over the buffer layer. The high-k dielectric layer may be, for example, hafnium oxide, zirconium oxide, or aluminum oxide. According to this exemplary embodiment, the method further comprises forming a gate electrode layer over the high-k dielectric layer. The gate electrode layer may be polycrystalline silicon, for example.
    Type: Grant
    Filed: January 20, 2004
    Date of Patent: July 4, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Joong S. Jeon, Robert B. Clark-Phelps, Qi Xiang, Huicai Zhong
  • Patent number: 6992370
    Abstract: According to one embodiment, a memory cell structure comprises a semiconductor substrate, a first silicon oxide layer situated over the semiconductor substrate, a charge storing layer situated over the first silicon oxide layer, a second silicon oxide layer situated over the charge storing layer, and a gate layer situated over the second silicon oxide layer. In the exemplary embodiment, the charge storing layer comprises silicon nitride having reduced hydrogen content, e.g., in the range of about 0 to 0.5 atomic percent. As a result, the reduced hydrogen content reduces the charge loss in the charge storing layer. The reduced charge loss in the charge storing layer has the benefit of reducing threshold voltage shifts, programming data loss, and programming capability loss in the memory device, thereby improving memory device performance.
    Type: Grant
    Filed: September 4, 2003
    Date of Patent: January 31, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: George J. Kluth, Robert B. Clark-Phelps, Joong S. Jeon, Huicai Zhong, Arvind Halliyal, Mark T. Ramsbey, Robert B. Ogle, Jr., Kuo T. Chang, Wenmei Li
  • Patent number: 6293845
    Abstract: A method and system for detecting a planarization endpoint of a semiconductor wafer planarization operation, which includes monitoring a motor current for at least one of a platen motor, a carousel motor and a head motor, performing a Fourier transform of the monitored current to identify periodic oscillations in the current, to ensure that undesirable oscillations in the monitored motor current are minimized, to provide better reliability and higher precision of end-point detection triggering.
    Type: Grant
    Filed: September 4, 1999
    Date of Patent: September 25, 2001
    Assignee: Mitsubishi Materials Corporation
    Inventor: Robert B. Clark-Phelps