Abstract: A current ramp generator is provided for controlling the fall time of a bubble generate waveform of a bubble memory system. Gate circuitry is responsive to a digital input signal and provides an initializing signal to a current source. The current source charges a capacitor and thereby provides an increasing signal to a current mirror whose output sinks current from a control amplifier of the bubble memory system.

Abstract: A sense amplifier which is fully integrated has an on-chip voltage regulator to provide essentially error free operation. The sense amplifier provides peak-to-peak signal detection for comparison to a threshold voltage by a comparator. The output of the comparator is coupled to an RS flip-flop. The output of the RS flip-flop is coupled to a D flip-flop. The use of an RS flip-flop as well as a D flip-flop eliminates clocking problems caused by skewing and keeps a stored detected signal from changing prematurely.

Abstract: A current amplifier uses a current mirror arrangement as an operational amplifier whose output has limited swing. The limited swing is achieved through a plurality of series connected diodes connected to a control input of the amplifier and to the output of the operational amplifier. The control input is coupled through a transistor to inhibit the output of the current mirror arrangement. The output node is coupled to an output for the current amplifier through a Darlington arrangement which provides high current gain.

Abstract: A circuit for providing the gate of a bubble memory with a precision current pulse at a high voltage is manufactured using a low voltage process; i.e. BV.sub.ceo is approximately 18 volts. In order to accomplish this, first and second voltage level shifting stages are cascoded and the output transistors thereof are used as Zener level shifters each level shifting downward by a BV.sub.ceo when only a small voltage is dropped across the load. If the voltage drop across the load increases, the cascoded output transistors may enter their active region and are prevented from going into saturation by saturation clamps so as to not introduce unwanted delays in the rise or fall times of the current pulse.

Abstract: In a voltage boost circuit for use in conjunction with a bubble memory operational driver, an output transistor alternately turns on and off so as to permit current to flow through an inductor which, when terminated by turning off the output transistor, causes a high voltage to be built up across the inductor which causes charge to be transferred to and stored in a capacitor. The output transistor is not turned on again until the voltage across the inductor falls below a predetermined value. A current mirror circuit is coupled to the comparator input and includes a buffer transistor which, when the voltage at the comparator input exceeds the break-down voltage of the buffer transistor, acts as a BV.sub.ceo level shifter.

Abstract: A solid state circuit for providing a DC regulated output voltage at an output thereof wherein the circuit exhibits excellent ripple rejection performance to maintain the regulated output voltage constant with perturbations in the supply voltage applied to the circuit. The circuit includes a precision current source for providing output currents to a load circuit which is connected between the current source and ground reference. A bias reference potential is applied to the load circuit which has an output connected to the output of the circuit and a feedback loop for causing the DC regulated voltage to be proportional to the bias reference potential. A frequency compensation circuit is included that is coupled across outputs of the current source which enhances the ripple rejection performance of the circuit to higher frequency component transients of such perturbations in the supply voltage.

Abstract: A circuit for providing a current at an output thereof of a predetermined value which has excellent ripple rejection characteristics whereby the magnitude of the current is maintain substantially constant with variations in the voltage supply applied thereto. The current source includes first and second complementary current mirror circuits interconnected such that the second current mirror sinks the current sourced from the first current mirror. A feedback loop latches the circuit into a stable operation and senses any difference current between the two current mirror circuits caused by perturbations of the supply voltage to produce feedback to maintain the circuit at its quiescent operating point.

Abstract: A circuit for providing a quiescent output voltage having a load resistor, a current means for establishing a load current through the load resistor, and a mirror means for summing a mirror current with the load current at an output terminal. The current means comprises a differential amplifier driving a multiplying mirror. The mirror means comprises a Wilson mirror for providing one of its tail currents as the additional current to be summed at the output terminal. The circuit provides a quiescent output voltage that is independent of the reference voltage supplying the differential amplifier or the tail current through the differential amplifier.

Abstract: A gated current source includes a first current source for generating a first current which is supplied to the anode of a diode. A second switched current source is also coupled to the anode of the diode and produces a second current which is greater than the first current. When the switched current source is off, a current is supplied to an output node via the diode. When the switched current source is on, a different current is pulled from the the output node via a transistor having a base coupled to the output node and an emitter coupled to the anode of the diode.

Abstract: An integrated voltage regulator circuit for providing a DC regulated output voltage which rejects perturbations in the supply voltage, comprising a current source, and a load circuit coupled with outputs of the current source which is referenced to ground potential, and a frequency compensation circuit coupled across the current source which increases the frequency response of the voltage regulator circuit. The current source includes first and second interconnected complementary type current mirrors wherein said first current mirror comprises a plurality of PNP current sourcing transistors having commonly connected bases. The bases of the PNP transistors are coupled to an external terminal. An external capacitor is connected between the external terminal and the supply voltage to overcome parasitic base-substrate capacitance inherent to the PNP transistors and improve the circuits ripple rejection performance.

Abstract: A method for achieving active devices with closely matched characteristics for use in high performance monolithic integrated circuits. The method comprises providing active devices with appropriately segmented junction regions connected in parallel by their metallic links and severing one or more of the links in order to achieve matching of both the static and dynamic characteristics of two or more active devices.

Abstract: A clamp circuit is disclosed which includes a transistor connected between the multiple collectors of a bias current device for complementary output transistors and the output terminal of a driver circuit. The clamp transistor is rendered conductive by signals at the output terminal of the driver circuit which would otherwise heavily saturate the bias current device. The clamp transistor conducts current to provide additional needed bias to the complementary output device and to keep such current from disturbing the magnitudes of currents provided by a current generator circuit which is also connected to the bias current device.

Abstract: A combination capacitor and transistor structure is described wherein the capacitor is formed integrally with the emitter electrode of the transistor. The transistor is formed in a monolithic integrated circuit using generally known techniques and constitutes a vertically integrated PNP device. The emitter electrode of the transistor which comprises a P+ diffusion region is of a predetermined area which is large enough to form the bottom plate of the capacitor. The top plate of the capacitor is formed by growing a dielectric material over the diffused emitter region and then forming metallization thereover. The combination capacitor and transistor structure may be utilized in a bias network for biasing the output stage of an operational amplifier in a class AB mode. The capacitor formed in the combination structure may be utilized as the compensation capacitor in such operational amplifier which utilizes pole splitting techniques.

Abstract: The disclosed amplifier includes first and second gain stages and first and second frequency compensating capacitors. The second gain stage has a first high impedance node coupled to the first gain stage, a second high impedance node, a first circuit coupled between the first and second high impedance nodes, a third high impedance node, and a second circuit coupled between the second and third high impedance nodes. The impedances at the first, second and third high impedance nodes are a function of frequency and the impedance at the second high impedance node is lower at any given frequency than the impedances at the first and third high impedance nodes. The first frequency compensating capacitor is coupled between the first and third nodes and the second frequency compensating capacitor is coupled between the third and second nodes.