Abstract: Some embodiments include an integrated assembly having bottom electrodes coupled with electrical nodes. Each of the bottom electrodes has a first leg electrically coupled with an associated one of the electrical nodes, and has a second leg joining to the first leg. First gaps are between some of the bottom electrodes, and second gaps are between others of the bottom electrodes. The first gaps alternate with the second gaps. Insulative material and conductive-plate-material are within the first gaps. Scaffold structures are within the second gaps and not within the first gaps. Capacitors include the bottom electrodes, regions of the insulative material and regions of the conductive-plate-material. The capacitors may be ferroelectric capacitors or non-ferroelectric capacitors. Some embodiments include methods of forming integrated assemblies.

Abstract: Some embodiments include an integrated assembly having bottom electrodes coupled with electrical nodes. Each of the bottom electrodes has a first leg electrically coupled with an associated one of the electrical nodes, and has a second leg joining to the first leg. First gaps are between some of the bottom electrodes, and second gaps are between others of the bottom electrodes. The first gaps alternate with the second gaps. Insulative material and conductive-plate-material are within the first gaps. Scaffold structures are within the second gaps and not within the first gaps. Capacitors include the bottom electrodes, regions of the insulative material and regions of the conductive-plate-material. The capacitors may be ferroelectric capacitors or non-ferroelectric capacitors. Some embodiments include methods of forming integrated assemblies.

Abstract: A high performance latch for read and write operations in RAM having a Complimentary Interlock circuit that eliminates the need for external timing to the RAM which might limit its high performance operation. For both read and write operations, the complementary interlock circuit extends a latching signal until valid data appears on the read or write data lines, thus preventing a valid data miss.