Patents by Inventor Robert B. Likovich, Jr.
Robert B. Likovich, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9436388Abstract: Memory access alignment in a double data rate (‘DDR’) system, including: executing, by a memory controller, one or more write operations to a predetermined address of a DDR memory module, including sending to the DDR memory module a predetermined amount of data of a predetermined pattern along with a data strobe signal; executing, by the memory controller, a plurality of read operations from the predetermined address of the DDR memory module, including capturing data transmitted from the DDR memory module; and determining, by the memory controller, a read adjust value and a write adjust value in dependence upon the data captured in response to the read operations.Type: GrantFiled: April 7, 2016Date of Patent: September 6, 2016Assignee: International Business Machines CorporationInventors: Steven K. Jenkins, Robert B. Likovich, Jr., Michael R. Trombley
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Publication number: 20160216897Abstract: Memory access alignment in a double data rate (‘DDR’) system, including: executing, by a memory controller, one or more write operations to a predetermined address of a DDR memory module, including sending to the DDR memory module a predetermined amount of data of a predetermined pattern along with a data strobe signal; executing, by the memory controller, a plurality of read operations from the predetermined address of the DDR memory module, including capturing data transmitted from the DDR memory module; and determining, by the memory controller, a read adjust value and a write adjust value in dependence upon the data captured in response to the read operations.Type: ApplicationFiled: April 7, 2016Publication date: July 28, 2016Inventors: STEVEN K. JENKINS, ROBERT B. LIKOVICH, JR., MICHAEL R. TROMBLEY
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Patent number: 9343123Abstract: Memory access alignment in a double data rate (‘DDR’) system, including: executing, by a memory controller, one or more write operations to a predetermined address of a DDR memory module, including sending to the DDR memory module a predetermined amount of data of a predetermined pattern along with a data strobe signal; executing, by the memory controller, a plurality of read operations from the predetermined address of the DDR memory module, including capturing data transmitted from the DDR memory module; and determining, by the memory controller, a read adjust value and a write adjust value in dependence upon the data captured in response to the read operations.Type: GrantFiled: September 10, 2014Date of Patent: May 17, 2016Assignee: International Business Machines CorporationInventors: Steven K. Jenkins, Robert B. Likovich, Jr., Michael R. Trombley
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Publication number: 20140379979Abstract: Memory access alignment in a double data rate (‘DDR’) system, including: executing, by a memory controller, one or more write operations to a predetermined address of a DDR memory module, including sending to the DDR memory module a predetermined amount of data of a predetermined pattern along with a data strobe signal; executing, by the memory controller, a plurality of read operations from the predetermined address of the DDR memory module, including capturing data transmitted from the DDR memory module; and determining, by the memory controller, a read adjust value and a write adjust value in dependence upon the data captured in response to the read operations.Type: ApplicationFiled: September 10, 2014Publication date: December 25, 2014Inventors: STEVEN K. JENKINS, ROBERT B. LIKOVICH, JR., MICHAEL R. TROMBLEY
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Patent number: 8902683Abstract: Memory access alignment in a double data rate (‘DDR’) system, including: executing, by a memory controller, one or more write operations to a predetermined address of a DDR memory module, including sending to the DDR memory module a predetermined amount of data of a predetermined pattern along with a data strobe signal; executing, by the memory controller, a plurality of read operations from the predetermined address of the DDR memory module, including capturing data transmitted from the DDR memory module; and determining, by the memory controller, a read adjust value and a write adjust value in dependence upon the data captured in response to the read operations.Type: GrantFiled: August 27, 2013Date of Patent: December 2, 2014Assignee: International Business Machines CorporationInventors: Steven K. Jenkins, Robert B. Likovich, Jr., Michael R. Trombley
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Publication number: 20130346686Abstract: Memory access alignment in a double data rate (‘DDR’) system, including: executing, by a memory controller, one or more write operations to a predetermined address of a DDR memory module, including sending to the DDR memory module a predetermined amount of data of a predetermined pattern along with a data strobe signal; executing, by the memory controller, a plurality of read operations from the predetermined address of the DDR memory module, including capturing data transmitted from the DDR memory module; and determining, by the memory controller, a read adjust value and a write adjust value in dependence upon the data captured in response to the read operations.Type: ApplicationFiled: August 27, 2013Publication date: December 26, 2013Applicant: International Business Machines CorporationInventors: STEVEN K. JENKINS, ROBERT B. LIKOVICH, JR., MICHAEL R. TROMBLEY
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Patent number: 8547760Abstract: Memory access alignment in a double data rate (‘DDR’) system, including: executing, by a memory controller, one or more write operations to a predetermined address of a DDR memory module, including sending to the DDR memory module a predetermined amount of data of a predetermined pattern along with a data strobe signal; executing, by the memory controller, a plurality of read operations from the predetermined address of the DDR memory module, including capturing data transmitted from the DDR memory module; and determining, by the memory controller, a read adjust value and a write adjust value in dependence upon the data captured in response to the read operations.Type: GrantFiled: June 29, 2011Date of Patent: October 1, 2013Assignee: International Business Machines CorporationInventors: Steven K. Jenkins, Robert B. Likovich, Jr., Michael R. Trombley
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Publication number: 20130003475Abstract: Memory access alignment in a double data rate (‘DDR’) system, including: executing, by a memory controller, one or more write operations to a predetermined address of a DDR memory module, including sending to the DDR memory module a predetermined amount of data of a predetermined pattern along with a data strobe signal; executing, by the memory controller, a plurality of read operations from the predetermined address of the DDR memory module, including capturing data transmitted from the DDR memory module; and determining, by the memory controller, a read adjust value and a write adjust value in dependence upon the data captured in response to the read operations.Type: ApplicationFiled: June 29, 2011Publication date: January 3, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Steven K. Jenkins, Robert B. Likovich, JR., Michael R. Trombley
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Patent number: 8212588Abstract: A bus system that includes a plurality of signal driving devices coupled to a common signal bus, a bus controlled circuit coupled to the common signal bus, and a compare circuit. The plurality of signal driving devices include a first signal driving device and a second signal driving device. The bus controller includes delay compensation circuitry with a configurable delay for each of the signal driving devices. The delay compensation circuitry has a current delay chain configuration associated with the first signal driving device. The compare circuit is configured to compare a first configurable delay associated with a first signal driving device to a second configurable delay associated with a second signal driving device of the plurality of signal driving devices, and for generating an output responsive to the comparing that indicates if the current delay chain configuration can be used by the second signal driving device.Type: GrantFiled: March 23, 2010Date of Patent: July 3, 2012Assignee: International Business Machines CorporationInventors: Theodore P. Haggis, Robert B. Likovich, Jr., James A. Mossman, Tiffany Tamaddoni-Jahromi, Robert B. Tremaine
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Patent number: 8196111Abstract: The present invention provides a method and system for providing a legal sequential combination of commands for verification testing of a computer system. Executable test commands are used to form sequentially ordered “buckets” of commands, wherein each bucket command sequence is legal under at least one rule. The buckets may be arranged in any sequential order, wherein a composite command sequence of the combined commands remains legal under the at least one rule. A further advantage of the invention is that wait/noop commands may be inserted within and between the buckets, extending the testing capabilities of the present invention into corner cases.Type: GrantFiled: January 11, 2008Date of Patent: June 5, 2012Assignee: International Business Machines CorporationInventors: David M. Atoji, Ruchi Chandra, Robert B. Likovich, Jr.
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Publication number: 20110234259Abstract: A bus system that includes a plurality of signal driving devices coupled to a common signal bus, a bus controlled circuit coupled to the common signal bus, and a compare circuit. The plurality of signal driving devices include a first signal driving device and a second signal driving device. The bus controller includes delay compensation circuitry with a configurable delay for each of the signal driving devices. The delay compensation circuitry has a current delay chain configuration associated with the first signal driving device. The compare circuit is configured to compare a first configurable delay associated with a first signal driving device to a second configurable delay associated with a second signal driving device of the plurality of signal driving devices, and for generating an output responsive to the comparing that indicates if the current delay chain configuration can be used by the second signal driving device.Type: ApplicationFiled: March 23, 2010Publication date: September 29, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Theodore P. Haggis, Robert B. Likovich, JR., James A. Mossman, Tiffany Tamaddoni-Jahromi, Robert B. Tremaine
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Publication number: 20090089728Abstract: Systems for using relative positioning of items or components in a structure with dynamic ranges, such as an elastic I/O bus design for an Integrated Circuit (IC), are disclosed. Embodiments may include a user-defined type module having user-defined types representing relative instance positions within a structure. Embodiments may also include a translation helper module to receive information associated with a hierarchy and to return location information associated with the hierarchy and a translation module to translate between a specific location and a relative position of the instance based on one or more user-defined types and location information returned from the translation helper module to generate a list of translated results. Further embodiments of the translation module may include a relative position determiner to translate specific locations to relative positions and may also include a specific location determiner to translate relative positions to specific locations.Type: ApplicationFiled: October 17, 2008Publication date: April 2, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Charles L. Alley, Robert B. Likovich, JR., Joseph D. Mendenhall, Chad E. Winemiller
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Patent number: 7461364Abstract: Methods and readable media for using relative positioning of items or components in a structure with dynamic ranges, such as an elastic I/O bus design for an Integrated Circuit (IC), are disclosed. Embodiments may include a user-defined type module having user-defined types representing relative instance positions within a structure. Embodiments may also include a translation helper module to receive information associated with a hierarchy and to return location information associated with the hierarchy and a translation module to translate between a specific location and a relative position of the instance based on one or more user-defined types and location information returned from the translation helper module to generate a list of translated results. Further embodiments of the translation module may include a relative position determiner to translate specific locations to relative positions and may also include a specific location determiner to translate relative positions to specific locations.Type: GrantFiled: April 10, 2006Date of Patent: December 2, 2008Assignee: International Business Machines CorporationInventors: Charles L. Alley, Robert B. Likovich, Jr., Joseph D. Mendenhall, Chad E. Winemiller
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Patent number: 7398515Abstract: The present invention provides a method and system for providing a legal sequential combination of commands for verification testing of a computer system. Executable test commands are used to form sequentially ordered “buckets” of commands, wherein each bucket command sequence is legal under at least one rule. The buckets may be arranged in any sequential order, wherein a composite command sequence of the combined commands remains legal under the at least one rule. A further advantage of the invention is that wait/noop commands may be inserted within and between the buckets, extending the testing capabilities of the present invention into corner cases.Type: GrantFiled: July 16, 2003Date of Patent: July 8, 2008Assignee: International Business Machines CorporationInventors: David M. Atoji, Ruchi Chandra, Robert B. Likovich, Jr.