Abstract: Systems, devices and methods are disclosed herein for reducing crosstalk between pairs of differential signal conductors. One or more ground traces connected to one or more over- or under-lying ground planes by vias are located between pairs of differential signal conductors. The electrical shielding provided by the combination of the one or more ground traces and the one or more ground planes results in reduced cross-talk between different pairs of differential signal conductors, and facilitates high-speed data rates between integrated circuits and printed circuit boards. In a preferred embodiment, such ground traces and ground planes are employed in HiTCE packaging containing multiple pairs of differential signal conductors.

Abstract: An apparatus for minimizing parasitic capacitance on a semiconductor die includes a semiconductor die having a least one signal line and at least one plane and an anti pad located between the at least one signal line and the at least one plane.

Abstract: Systems, devices and methods are disclosed herein for reducing crosstalk between pairs of differential signal conductors. One or more ground traces connected to one or more over- or under-lying ground planes by vias are located between pairs of differential signal conductors. The electrical shielding provided by the combination of the one or more ground traces and the one or more ground planes results in reduced cross-talk between different pairs of differential signal conductors, and facilitates high-speed data rates between integrated circuits and printed circuit boards. In a preferred embodiment, such ground traces and ground planes are employed in HiTCE packaging containing multiple pairs of differential signal conductors.

Abstract: A non-linear digital-to-analog converter (non-linear "DAC") and method are disclosed for scaling a digital input value by a non-integer and producing an analog output. The digital input value is multiplied by a non-integer, and the integer portion of the result is fed to a linear DAC to produce a linear analog output. At least one of the bits of the integer portion of the result is decoded, and at least one compensation value is generated responsive to the decoding. The compensation value is added to the linear analog output and represents the fractional portion of the result of scaling the digital input value by the non-integer. A method is also disclosed for utilizing the non-linear DAC for error compensation in a computer graphics system. Color intensity values are scaled up by a non-integer greater than one. A first analog output is generated proportional to the integer portion of the result.

Abstract: Adverse visual effects on a video display caused by switching operations in a digital-to-analog converter of the video subsystem and by parasitic impedance loading the DAC are minimized. Current cells associated with the DAC generate discrete currents for the video display. Each current cell has a current source for providing a current continuously and first and second switching mechanisms. The first switching mechanism is actuated by a select signal for switching the current to a current sink having a dummy resistance R.sub.d, and the second switching mechanism is actuated by an nselect signal for switching the current to the video display. The select and nselect signals, are generated from input data. A first feedback loop combines the select signal with the data to derive the nselect signal so that the nselect signal is generated after the select signal decreases to a predefined threshold, preferably zero.

Abstract: A CMOS circuit for converting voltage levels between shifted differential ECL voltage level input signals and a CMOS voltage level signal. The ECL levels are referenced to the VDD voltage of the CMOS circuit and can be connected to ECL circuits that are connected between the CMOS VDD voltage and ground. The circuit has a pFET connected between a supply voltage and the output signal, and an nFET connected between the output signal and circuit ground. An inverted signal of the differential shifted ECL voltage input signals is connected to a gate of the nFET. A level shifting circuit connects the input signals to a gate of the pFET to ensure that it correctly drives the output signal when the input signals change logic levels.

Abstract: Multiple punchthru devices are coupled between multiple metal-two conductors and a metal-one bond pad. Each punchthru device has the capacity to couple its respective metal-two conductor to the bond pad when a predetermined voltage potential exists between the metal-two conductor and the bond pad. A set of metal-one islands, one set associated with each metal-one bond pad cell, resides in a bond pad channel. The positioning of the punchthru devices and the islands minimizing the bond pad cell size and minimizing the spacing between adjacent bond pad cells. The bond pad cell configuration also allows any metal-two conductor to be coupled to the bond pad without having to rearrange punchthru devices or reconfigure the bond pad cell. The multiple punchthru devices associated with each bond pad cell provide redundant overvoltage protection superior to present overvoltage protection circuits.

Abstract: A CMOS level conversion circuit for converting voltage levels between CMOS levels and shifted ECL levels, where the shifted ECL levels are referenced to the VDD supply voltage of the CMOS circuit. The circuit contains a pFET connected between the VDD supply voltage and the output terminal and an nFET connected between the output terminal and circuit ground. The input signal is connected to the gate input of the nFET. A second pFET is connected in parallel to the nFET between the output terminal and ground. A bias voltage is supplied to the gate inputs of both pFETs, to cause the output terminal to have a shifted ECL logic one voltage when the gate to the nFET is low. The pFETs are fabricated within the integrated circuit to be located very close to each other to compensate for variations in the CMOS integrated circuit manufacturing process.

Abstract: A process is described for electrically interconnecting electronic devices located on a surface through one or more planar linking layers consisting of conductors and dielectrics. A three-step additive process is disclosed for forming each planar linking layer. The process may be repeated in order to form the multiple linking layers required for complex VLSI circuits. Each layer is formed by a three step process of applying a uniform dielectric, removing the dielectric where the interconnections, including vias and lines, are to be made and then selectively depositing a conductor to form the interconnections.

Abstract: An undersea plow is towed by a surface vessel to inscribe a pattern of marks on a marine bottom of questionable soil stability. The plow digs a trench large enough to be seen by sidescan sonar but does not bury itself so far in the soft soil that it cannot be towed at a reasonable rate. The plow is symmetrical about a horizontal line parallel to the path of the trench so that regardless of how the plow comes to rest when lowered, it will still dig the trench. Periodic sidescan surveys detect bottom soil movements by mapping changes in the pattern of marks created by the plow.