Abstract: The present disclosure generally relates to displaying information related to a physical activity. In some embodiments, methods and user interfaces for managing the display of information related to a physical activity are described.

Abstract: Apparatus and method for use in a multiprocessor system (10) having a plurality of processing nodes (P0-P3) each of which includes a local data processor (22a, 28a). The apparatus includes an interface (42) to a controller (14), the interface including a register (48) for storing a function received from the controller, such as a diagnostic function. The interface further includes circuitry (50) for providing the diagnostic function as a packet to an input terminal of a bit serial communication bus (40). The communication bus is threaded through each of the plurality of processing nodes and has an output terminal that terminates at the interface.

Abstract: A multiprocessor data processing system (10), and a method of operating same, so as to provide efficient bandwidth utilization of shared system resources (24, 26). The system includes a plurality of processor nodes, each of which includes a data processor (22a, 28a). A first step of a method buffers data written by a data processor to a first bus (23a), prior to the data being transmitted to a second bus (32). Also buffered are byte enable (BE) signals generated by the data processor in conjunction with the data written by the data processor. A next step performs a main memory (26) write operation by transmitting the buffered data to the second bus; responsive to the stored BE signals, also transmitting a control signal for indicating if a memory write is to be accomplished as a read-modify-write (RMW) type of memory operation; and transmitting the stored BE signals to the second bus.

Abstract: An I/O Processor (28) includes a two channel receiver (28b) and a two channel transmitter (28c) coupled to a high speed communications channel. For the receiver a status memory, specifically a FIFO (44a, 44b), stores structuring information that indicates the beginnings (SOP) and endings (EOP) of PACKETS, as well as, for each BURST of data words within a packet, an indication of the occurrence of the BURST and a length (L) of the BURST. Additionally, there is an indication for each BURST of the presence of any errors occurring during the BURST. A corresponding data FIFO (40a, 40b) contains only the received data words, without any structuring information. A device reads both of the FIFOS, subsequent to the reception of one or more PACKETS, so as to reconstruct the original format of the received data.

Abstract: A camera apparatus for detecting code indicia in the form of a series of electrically conductive areas located on the exterior of a film cartridge, includes a loading chamber adapted to receive the cartridge and a plurality of metallic probes which protrude slightly into the chamber to make electrical contact with at least some of the conductive areas of the cartridge. According to the invention, an electrically insulative mounting block has respective securement means equal in actual number to a predetermined number of the conductive areas of the cartridge for permitting the probes to be manually secured selectively to the mounting block, whereby only a minimum number of the probes required for the camera apparatus which is less than the actual number of the securement means need be included in the assembly.

Abstract: A catalyst/substrate delivery system providing a more efficient combustion of hydrocarbon fuels while reducing environmental pollutants emitting therefrom. A light hydrocarbon is misted into a cold environment to form frozen pellets which are then coated with plasma of an atomized catalyst such as platinum, palladium, lithium, zirconium organometals to form microspheres of from about 1 but less than 2000 microns in size.

Abstract: An instruction sequencer for programming parallel operations of functional units in response to an instruction stream is shown. The instruction sequencer includes a random access memory for storing instruction segments which program the operations of the functional units. An instruction address register contains instruction addresses for selected locations in the memory having instruction segments stored therein. A memory address circuit reads out an instruction stream comprising instruction segments from the memory in response to the stored instruction address and stores the same in an instruction buffer register. A rotating network, which is operatively coupled to the instruction buffer register, rotates the instruction stream so as to position a selected instruction segment at a predetermined location in a rotating network.