Abstract: The present invention describes the formation of a silicide layer upon a gate conductor by using a masking layer which covers the source/drain regions of the transistor. The method includes forming a masking layer over a semiconductor substrate such that the gate conductor is substantially covered by the masking layer. The masking layer is preferably planarized using any of a variety of well known techniques. After planarization of the masking layer, the masking layer is etched such that an upper surface of the gate conductor is exposed. A silicide layer is preferably formed upon the upper surface of the gate conductor. The masking layer prevents the concurrent formation of silicide upon the source/drain regions.

Abstract: A reference cell in a nonvolatile memory is electrically erasable and the electrically erasable character of the memory is exploited to expand the voltage range over which a differential amplifier is useful for sensing the state of a bit. Selected elements of a reference cell are electrically erased and reprogrammed for accurately tuning the sensing of multiple data states in a memory cell. For example, 64 or more data states may be tuned so that a single megabyte of memory is allocated to store six megabytes of information.

Abstract: A storage control circuit determines a programmed threshold voltage V.sub.tP of a storage cell in which the transistor threshold voltages V.sub.tT of the cell may overlap while the logical threshold voltages V.sub.tL remain distinct. In one embodiment, sixteen distinctive levels are stored in a storage cell within a 2.5 V range so that a single memory cell supplies four bits of information storage per cell, quadrupling the memory capacity per cell as compared to conventional single-bit storage cells. In an embodiment, a nonvolatile memory circuit includes a nonvolatile memory array with a plurality of memory cells and a plurality of decoders connected to the nonvolatile memory array. The plurality of decoders decode addresses to the nonvolatile memory array.

Abstract: A non-volatile memory device is provided having an array of single transistor memory cells read in accordance with an improved read cycle operation. That is, a selected cell mutually connected via a single bit line to other cells is assured activation necessary to discern a programmed or unprogrammed state of that cell. The non-selected cells connected to the selected cell are advantageously assured of non-activation by applying a negative voltage to the word lines associated with those cells. The negative voltage is less than the threshold voltage associated with the single transistor MOS device. The non-selected cells are thereby retained inactive to provide a singular active or inactive selected cell dependent solely upon the programmed state of the array. Negative voltage upon the non-selected cells provides minimal leakage of over-erased cells normally associated with depletion mode operation.

Abstract: A non-volatile memory device is provided having various electrical couplings for maximizing over-erased correction of that device. Over-erased devices within an array can be corrected in bulk, simultaneous with all other devices within the array. Bulk correction of an array of over-erased device is carried forth in a convergence technique which utilizes higher floating gate injection currents. Negatively biased substrate causes an enhancement in the injection current and resulting correction capability of the convergence operation. Moreover, convergence can be carried out with a lesser positive voltage upon the drain region, which implies a reduction in the source-to-drain currents as well as substrate currents during the convergence operation. Accordingly, only over-erased transistors receive sufficient turn-on during convergence, while all other transistors remain off.

Abstract: An MOS device is provided having a drain- or source-side implant into the channel region in order to minimize short-channel effects. Implant into the channel region is achieved using conventional processing techniques, wherein the channel implant is directed substantially perpendicular to the upper surface of the substrate. Numerous masking steps and reorientation of the substrate is not needed. Additionally, the drain- or source-side implant mask can be formed from currently existing masks and incorporated into a standard processing flow for either a standard MOS device or a memory array comprising dual-level polysilicon. If drain-side implant is chosen, then the lateral demarcation line between the drain implant and the substrate is preferably placed within the channel region, and preferably near a mid-point within the channel a spaced distance below a subsequently placed, overlying polysilicon.

Abstract: A flash EPROM device is provided for programmably storing digital data within a core array of electrically programmable transistors. A row or column within the array can be substituted for a spare or redundant row or column selectively connected to row or column decoder circuits by a redundancy select transistor. Self-aligned source regions within the array and redundancy select area are provided using a single mask for opening the self-aligned source regions and for implanting a light dosage of phosphorus directly into the underlying silicon substrate. Careful control and elimination of residue within the etched area via a subsequent wet etch helps ensure the implant edges are anisotropically controlled and isolated for subsequent lateral diffusion/drive-in. Accordingly, the flash EPROM device of a plurality of transistors within the array and within the redundancy select area are process controlled and demonstrate a significant reduction in threshold skewing.