Abstract: A cascaded interconnect system including a memory controller, one or more memory modules, an upstream memory bus and a downstream memory bus. The one or more memory modules include a first memory module with cache data. The memory modules and the memory controller are interconnected by a packetized multi-transfer interface via the downstream memory bus and the upstream memory bus. The first memory module and the memory controller are in direct communication via the upstream memory bus and the downstream memory bus.

Abstract: A method for reconfiguring a cache memory is provided. The method in one aspect may include analyzing one or more characteristics of an execution entity accessing a cache memory and reconfiguring the cache based on the one or more characteristics analyzed. Examples of analyzed characteristic may include but are not limited to data structure used by the execution entity, expected reference pattern of the execution entity, type of an execution entity, heat and power consumption of an execution entity, etc. Examples of cache attributes that may be reconfigured may include but are not limited to associativity of the cache memory, amount of the cache memory available to store data, coherence granularity of the cache memory, line size of the cache memory, etc.

Abstract: Memory systems are disclosed that include a memory controller; an outbound link, the memory controller connected to the outbound link, the outbound link comprising a number of conductive pathways that conduct memory signals from the memory controller to memory buffer devices in a first memory layer; and at least two memory buffer devices in a first memory layer, each memory buffer device in the first memory layer connected to the outbound link to receive memory signals from the memory controller.

Abstract: A cascaded interconnect system including a memory controller, one or more memory modules, an upstream memory bus and a downstream memory bus. The one or more memory modules include a first memory module with cache data. The memory modules and the memory controller are interconnected by a packetized multi-transfer interface via the downstream memory bus and the upstream memory bus. The first memory module and the memory controller are in direct communication via the upstream memory bus and the downstream memory bus.

Abstract: Memory systems are disclosed that include a memory controller and an outbound link with the memory controller connected to the outbound link. The outbound link typically includes a number of conductive pathways that conduct memory signals from the memory controller to memory buffer devices in a first memory layer; and at least two memory buffer devices in a first memory layer. Each memory buffer device in the first memory layer typically is connected to the outbound link to receive memory signals from the memory controller.

Abstract: Design structures for program directed memory access patterns. A design structure is embodied in a machine readable medium used in a design process, the design structure including a computer memory system for storing and retrieving data. The memory system includes a memory, a memory controller and a virtual memory management system. The memory includes a plurality of memory devices organized into one or more physical groups accessible via associated busses for transferring data and control information. The memory controller receives and responds to memory access requests that contain application access information to control access pattern and data organization within the memory. Responding to memory access request includes accessing one or more memory devices.

Abstract: A method for reconfiguring a cache memory is provided. The method in one aspect may include analyzing one or more characteristics of an execution entity accessing a cache memory and reconfiguring the cache based on the one or more characteristics analyzed. Examples of analyzed characteristic may include but are not limited to data structure used by the execution entity, expected reference pattern of the execution entity, type of an execution entity, heat and power consumption of an execution entity, etc. Examples of cache attributes that may be reconfigured may include but are not limited to associativity of the cache memory, amount of the cache memory available to store data, coherence granularity of the cache memory, line size of the cache memory, etc.

Abstract: A method and system for providing quality of service guarantees for simultaneous multithreaded processors are disclosed. Hardware and operating system communicate with one another providing information relating to thread attributes for threads executing on processing elements. The operating system controls scheduling of the threads based at least partly on the information communicated and provides quality of service guarantees.

Abstract: Design structures embodied in machine readable medium are provided. Embodiments of the design structure include a memory system comprising: a memory controller; a memory bus terminator; a high speed memory bus that interconnects the memory controller, the memory bus terminator, and at least one memory module; and the at least one memory module, the memory module comprising at least one memory hub device, high speed random access memory served by the memory hub device, two bus signal ports, and a segment of the high speed memory bus fabricated on the memory module so as to interconnect the bus signal ports and the memory hub device, the high speed memory bus connected to the memory hub device by a negligible electrical stub.

Abstract: A solution for cooperative data prefetching that enables software control of a memory-side data prefetch and/or a processor-side data prefetch is provided. In one embodiment, the invention provides a solution for generating an application, in which access to application data for the application is improved (e.g., optimized) in program code for the application. In particular, a push request, for performing a memory-side data prefetch of the application data, and a prefetch request, for performing a processor-side data prefetch, are added to the program code. The memory-side data prefetch results in the application data being copied from a first data store to a second data store that is faster than the first data store while the processor-side data prefetch results in the application data being copied from the second data store to a third data store that is faster than the second data store.

Abstract: Systems and methods for providing distributed autonomous power management in a memory system. Embodiments include a memory system for storing and retrieving data for a processing system. The memory system includes a memory controller for receiving and responding to memory access requests, a memory bus in communication with the memory controller, a plurality of memory devices, and a control unit external to the memory controller. The memory devices are in communication with the memory controller via the memory bus, with one or more of the memory devices being associated with a group. The control unit autonomously manages power within and for the group of memory devices.

Abstract: Systems and methods for determining memory module power requirements in a memory system. Embodiments include a memory system with a physical memory and a memory controller. The physical memory includes a plurality of memory devices. The memory controller is in communication with the physical memory and has a logical memory for storing power usage characteristics associated with the physical memory. The power usage characteristics are generated in response to a current operating environment of the memory system.

Abstract: A method and system for thread scheduling for optimal heat dissipation are provided. Temperature sensors measure temperature throughout various parts of a processor chip. The temperatures detected are reported to an operating system or the like for scheduling threads. In one aspect, the observed temperature values are recorded on registers. An operating system or the like reads the registers and schedules threads based on the temperature values.

Abstract: A method and system for providing quality of service guarantees for simultaneous multithreaded processors are disclosed. Hardware and operating system communicate with one another providing information relating to thread attributes for threads executing on processing elements. The operating system controls scheduling of the threads based at least partly on the information communicated and provides quality of service guarantees.

Abstract: A method for reconfiguring a cache memory is provided. The method in one aspect may include analyzing one or more characteristics of an execution entity accessing a cache memory and reconfiguring the cache based on the one or more characteristics analyzed. Examples of analyzed characteristic may include but are not limited to data structure used by the execution entity, expected reference pattern of the execution entity, type of an execution entity, heat and power consumption of an execution entity, etc. Examples of cache attributes that may be reconfigured may include but are not limited to associativity of the cache memory, amount of the cache memory available to store data, coherence granularity of the cache memory, line size of the cache memory, etc.

Abstract: Memory systems are disclosed that include a memory controller and an outbound link with the memory controller connected to the outbound link. The outbound link typically includes a number of conductive pathways that conduct memory signals from the memory controller to memory buffer devices in a first memory layer; and at least two memory buffer devices in a first memory layer. Each memory buffer device in the first memory layer typically is connected to the outbound link to receive memory signals from the memory controller.

Abstract: Systems and methods for providing remote pre-fetch buffers. The systems include a computer memory system with a memory controller, one or more memory busses connected to the memory controller, and at least one memory subsystem in communication with the memory controller via the memory busses. The memory controller generates, receives and responds to memory access requests including unsolicited data transfers. The memory subsystem includes one or more memory devices and logic to initiate an unsolicited data transfer to the memory controller based on analysis performed at the memory subsystem of prior memory access requests received by the memory subsystem.

Abstract: Memory systems are disclosed that include a memory controller; a memory bus terminator; a high speed memory bus that interconnects the memory controller, the memory bus terminator, and at least one memory module, where memory module includes a memory hub device, high speed random access memory served by the memory hub device, two bus signal ports, and a segment of the high speed memory bus fabricated on the memory module so as to interconnect the bus signal ports and the memory hub device, with the high speed memory bus connected to the memory hub device by a negligible electrical stub.

Abstract: Systems and methods for providing data modification operations in memory subsystems. Systems include a plurality of memory devices, a memory controller, one or more memory busses connected to the memory controller and a memory hub device. The memory controller receives and responds to memory access requests including memory update requests from a processor. The memory controller also generates a memory update command in response to receiving a memory update request. The memory hub device includes a first port, a second port and a control unit. The first port is in communication with the memory controller via one or more of the memory busses for transferring data and control information between the memory hub device and the memory controller. The second port is in communication with one or more of the memory devices.

Abstract: Systems and methods for providing distributed technology independent memory controllers. Systems include a computer memory system for storing and retrieving data. The system includes a memory bus, a main memory controller, one or more memory devices characterized by memory device protocols and signaling requirements, and one or more memory hub devices. The main memory controller is in communication with the memory bus for generating, receiving, and responding to memory access requests. The hub devices are in communication with the memory bus and with the memory devices for controlling the memory devices responsively to the memory access requests received from the main memory controller and for responding to the main memory controller with state or memory data.