Patents by Inventor Robert B. Turkot, Jr.

Robert B. Turkot, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200075334
    Abstract: An integrated circuit die including tight pitch features and a method of fabricating an integrated circuit die using subtractive patterning by asymmetric spacer formation is disclosed. The integrated circuit die a substrate and a first multitude of features above the substrate. The integrated circuit die includes a second multitude of features above the substrate. The first multitude of features and the second multitude of features are same features disposed in a first direction. The first multitude of features interleave with the second multitude of features. The first multitude of features has a first size and the second multitude of features has a second size.
    Type: Application
    Filed: March 31, 2017
    Publication date: March 5, 2020
    Inventors: Richard E. SCHENKER, Robert B. TURKOT, Jr.
  • Publication number: 20200066967
    Abstract: Damascene-based approaches for fabricating a pedestal for a magnetic tunnel junction (MTJ) device, and the resulting structures, are described. In an example, a magnetic tunnel junction (MTJ) device includes a metal line disposed in a dielectric layer disposed above a substrate, the metal line recessed below an uppermost surface of the dielectric layer. The MTJ device also includes a conductive pedestal disposed on the metal line and laterally adjacent to the dielectric layer. The MTJ device also includes a magnetic tunnel junction (MTJ) stack disposed on the conductive pedestal.
    Type: Application
    Filed: March 31, 2016
    Publication date: February 27, 2020
    Inventors: Satyarth SURI, Tejaswi K. INDUKURI, Robert B. TURKOT, JR., James S. CLARKE
  • Publication number: 20170005176
    Abstract: The present disclosure relates to a method of etching sacrificial material. The method includes supplying a semiconductor substrate in a reaction chamber, wherein the substrate includes a channel disposed on the substrate and a sacrificial layer disposed on at least a portion of the channel. The method further includes supplying an interhalogen vapor to the reaction chamber, etching at least a portion of the sacrificial layer with the interhalogen vapor and exposing at least a portion of said channel from under the sacrificial layer.
    Type: Application
    Filed: December 27, 2013
    Publication date: January 5, 2017
    Applicant: Intel Corporation
    Inventors: SEUNG HOON SUNG, ROBERT B. TURKOT, JR., ANAND S. MURTHY, SEIYON KIM, KELIN J. KUHN
  • Publication number: 20140091279
    Abstract: Non-planar semiconductor devices having germanium-based active regions with release etch-passivation surfaces are described. For example, a semiconductor device includes a vertical arrangement of a plurality of germanium-rich nanowires disposed above a substrate. Each nanowire includes a channel region having a sulfur-passivated outer surface. A gate stack is disposed on and completely surrounds the channel region of each of the germanium-rich nanowires. The gate stack includes a gate dielectric layer disposed on and surrounding the sulfur-passivated outer surface and a gate electrode disposed on the gate dielectric layer. Source and drain regions are disposed on either side of the channel regions of the germanium-rich nanowires.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Inventors: Jessica S. Kachian, Willy Rachmady, Robert B. Turkot, Jr.
  • Patent number: 8017568
    Abstract: Supercritical carbon dioxide may be utilized to remove resistant residues such as those residues left when etching dielectrics in fluorine-based plasma gases. The supercritical carbon dioxide may include an oxidizer in one embodiment.
    Type: Grant
    Filed: February 28, 2003
    Date of Patent: September 13, 2011
    Assignee: Intel Corporation
    Inventors: Shan C. Clark, Vijayakumar S. Ramachandrarao, Robert B. Turkot, Jr.
  • Patent number: 7387927
    Abstract: A metal layer is formed on a dielectric layer, which is formed on a substrate. After forming a masking layer on the metal layer, the exposed sides of the dielectric layer are covered with a polymer diffusion barrier.
    Type: Grant
    Filed: September 10, 2004
    Date of Patent: June 17, 2008
    Assignee: Intel Corporation
    Inventors: Robert B. Turkot, Jr., Justin K. Brask, Jack Kavalieros, Mark L. Doczy, Matthew V. Metz, Uday Shah, Suman Datta, Robert S. Chau
  • Patent number: 7233068
    Abstract: Suitable particles may be deposited within an extremely small high-aspect ratio via by flowing the particles in a suspension using supercritical carbon dioxide. The particles may be made up of diblock copolymers or silesquioxane-based materials or oligomers of phobic homopolymers or pre-formed silica-based particles stabilized using diblock copolymers and may include chemical initiators to permit in situ polymerization within the via.
    Type: Grant
    Filed: September 17, 2004
    Date of Patent: June 19, 2007
    Assignee: Intel Corporation
    Inventors: Vijayakumar S. Ramachandrarao, Robert B. Turkot, Jr.
  • Patent number: 7129182
    Abstract: A method for etching a metal layer is described. That method comprises forming a metal layer on a substrate, then exposing part of the metal layer to a wet etch chemistry that comprises an active ingredient with a diameter that exceeds the thickness of the metal layer.
    Type: Grant
    Filed: November 6, 2003
    Date of Patent: October 31, 2006
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Mark L. Doczy, Jack Kavalieros, Uday Shah, Matthew V. Metz, Robert S. Chau, Robert B. Turkot, Jr.
  • Patent number: 7056780
    Abstract: A metal silicide may be selectively etched by converting the metal silicide to a metal silicate. This may be done using oxidation. The metal silicate may then be removed, for example, by wet etching. A non-destructive low pH wet etchant may be utilized, in some embodiments, with high selectivity by dissolution.
    Type: Grant
    Filed: July 18, 2003
    Date of Patent: June 6, 2006
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Robert B. Turkot, Jr.
  • Patent number: 7045428
    Abstract: A method for making a semiconductor device is described. That method comprises forming on a substrate a first gate dielectric layer that has a first substantially vertical component, then forming a first metal layer on the first gate dielectric layer. After forming on the substrate a second gate dielectric layer that has a second substantially vertical component, a second metal layer is formed on the second gate dielectric layer. In this method, a conductor is formed that contacts both the first metal layer and the second metal layer.
    Type: Grant
    Filed: May 26, 2004
    Date of Patent: May 16, 2006
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Jack Kavalieros, Mark L. Doczy, Matthew V. Metz, Uday Shah, Chris E. Barns, Suman Datta, Robert B. Turkot, Jr., Robert S. Chau
  • Patent number: 7037845
    Abstract: A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer on a substrate, and modifying a first portion of the high-k gate dielectric layer to ensure that it may be removed selectively to a second portion of the high-k gate dielectric layer.
    Type: Grant
    Filed: August 28, 2003
    Date of Patent: May 2, 2006
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Uday Shah, Mark L. Doczy, Jack Kavalieros, Robert S. Chau, Robert B. Turkot, Jr., Matthew V. Metz
  • Patent number: 7022655
    Abstract: Supercritical carbon dioxide may be utilized to remove resistant residues such as those residues left when etching dielectrics in fluorine-based plasma gases. The supercritical carbon dioxide may include an ionic liquid in one embodiment.
    Type: Grant
    Filed: June 4, 2003
    Date of Patent: April 4, 2006
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Robert B. Turkot, Jr., Vijayakumar S. Ramachandrarao
  • Patent number: 6974764
    Abstract: A method for making a semiconductor device is described. That method comprises forming a dielectric layer on a substrate, and forming a first metal layer on a first part of the dielectric layer, leaving a second part of the dielectric layer exposed. After a second metal layer is formed on both the first metal layer and the second part of the dielectric layer, a masking layer is formed on the second metal layer.
    Type: Grant
    Filed: November 6, 2003
    Date of Patent: December 13, 2005
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Mark L. Doczy, Jack Kavalieros, Uday Shah, Matthew V. Metz, Robert S. Chau, Robert B. Turkot, Jr.
  • Patent number: 6896774
    Abstract: Metal may be deposited into trenches, vias, or other wafer openings using a physical vapor deposition chamber under vacuum. Sonic energy may be applied directly to the wafer having the openings to be filled. As a result, pinching off of the openings may be reduced or eliminated.
    Type: Grant
    Filed: March 6, 2003
    Date of Patent: May 24, 2005
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Mark L. Doczy, Robert B. Turkot, Jr.
  • Patent number: 6812132
    Abstract: Suitable particles may be deposited within an extremely small high-aspect ratio via by flowing the particles in a suspension using supercritical carbon dioxide. The particles may be made up of diblock copolymers or silesquioxane-based materials or oligomers of phobic homopolymers or pre-formed silica-based particles stabilized using diblock copolymers and may include chemical initiators to permit in situ polymerization within the via.
    Type: Grant
    Filed: March 21, 2003
    Date of Patent: November 2, 2004
    Assignee: Intel Corporation
    Inventors: Vijayakumar S. Ramachandrarao, Robert B. Turkot, Jr.
  • Patent number: 6624127
    Abstract: Supercritical carbon dioxide may be utilized to remove resistant residues such as those residues left when etching dielectrics in fluorine-based plasma gases. The Supercritical carbon dioxide may include an ionic liquid in one embodiment.
    Type: Grant
    Filed: November 15, 2002
    Date of Patent: September 23, 2003
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Robert B. Turkot, Jr., Vijayakumar S. Ramachandrarao