Abstract: Methods of operating a memory device are useful in managing wear leveling operations. Such methods include receiving an instruction from a host device in communication with the memory device, wherein the instruction comprises a command portion indicating a desire to identify portions of the memory device to be excluded from wear leveling operations and an argument portion comprising information identifying a particular group of one or more blocks of the plurality of blocks; storing the information identifying the particular group of one or more blocks to a non-volatile memory of the memory device as a portion of information identifying blocks to be excluded from wear leveling operations; and performing one or more wear leveling operations only on a subset of the plurality of blocks responsive to the information identifying blocks to be excluded from wear leveling operation.

Abstract: Methods of operating a memory device are useful in managing wear leveling operations.

Abstract: Memory devices and methods to facilitate wear leveling operations in a memory device. In one such method, particular blocks of memory cells are excluded from experiencing wear leveling operations performed on the memory device. In at least one method, a user selects blocks of memory to be excluded from wear leveling operations performed on the remainder of blocks of the memory device. Selected blocks of memory are excluded from wear leveling operations responsive to a command initiated by a user identifying, either directly or indirectly, the selected blocks to be excluded.

Abstract: Memory devices and methods to facilitate wear leveling operations in a memory device. In one such method, particular blocks of memory cells are excluded from experiencing wear leveling operations performed on the memory device. In at least one method, a user selects blocks of memory to be excluded from wear leveling operations performed on the remainder of blocks of the memory device. Selected blocks of memory are excluded from wear leveling operations responsive to a command initiated by a user identifying, either directly or indirectly, the selected blocks to be excluded.

Abstract: An apparatus and method are disclosed for providing a kicker function for non-volatile memory drain bias. According to one embodiment, the kicker function is provided by a high performance transistor that is activated by a kicker enable signal, providing a kicker function for non-volatile memory drain bias. According to one embodiment, the kicker function is provided by a high performance transistor that is activated by a kicker enable signal.

Abstract: An apparatus is disclosed for providing a load for a non-volatile memory drain bias circuit. Under an embodiment, a load for a non-volatile memory drain bias circuit comprises a column load and a current mirror, a reference voltage for the current mirror being a sample and hold voltage reference. The column load and the current mirror are coupled to a cascode device.

Abstract: An apparatus and method are disclosed for providing drain bias for non-volatile memory. According to one embodiment, the drain bias is provided utilizing a drain bias circuit that is referenced by a static voltage reference.

Abstract: A method and apparatus for a memory device is described. In one embodiment, global Y (GY) enable is gated by the trailing edge of a address transition detection (ATD) pulse. The ATD pulse ensures that the GY enable is off during periods when the memory device is not attempting to read a memory cell. The sense (SEN) node between the GY transistor and drain bias circuit may be charged up and global bit line (GBL) may be grounded. During this time, the power supply current is cut off by the GY transistor itself, thereby eliminating the need of separate cut-off transistors within the drain bias circuit. This permits minimal time delay in sensing after the incoming address is stable.

Abstract: An apparatus and method are disclosed for providing a load for non-volatile memory drain bias. According to one embodiment, a load comprising a column load and a current mirror is referenced using a sample and hold voltage reference.

Abstract: An apparatus and method are disclosed for providing a sample and hold voltage reference for non-volatile memory. According to one embodiment, the sample and hold voltage reference produces a reference voltage for a drain bias circuit of a memory cell.

Abstract: A method and apparatus for a memory device is described. In one embodiment, global Y (GY) enable is gated by the trailing edge of a address transition detection (ATD) pulse. The ATD pulse ensures that the GY enable is off during periods when the memory device is not attempting to read a memory cell. The sense (SEN) node between the GY transistor and drain bias circuit may be charged up and global bit line (GBL) may be grounded. During this time, the power supply current is cut off by the GY transistor itself, thereby eliminating the need of separate cut-off transistors within the drain bias circuit. This permits minimal time delay in sensing after the incoming address is stable.

Abstract: An apparatus and method are disclosed for providing drain bias for non-volatile memory. According to one embodiment, the drain bias is provided utilizing a drain bias circuit that is referenced by a static voltage reference.

Abstract: An apparatus and method are disclosed for providing a sample and hold voltage reference for non-volatile memory. According to one embodiment, the sample and hold voltage reference produces a reference voltage for a drain bias circuit of a memory cell.

Abstract: An apparatus and method are disclosed for providing a kicker function for non-volatile memory drain bias. According to one embodiment, the kicker function is provided by a high performance transistor that is activated by a kicker enable signal. providing a kicker function for non-volatile memory drain bias. According to one embodiment, the kicker function is provided by a high performance transistor that is activated by a kicker enable signal.