Patents by Inventor Robert Bedichek
Robert Bedichek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9875103Abstract: A method for use by a host microprocessor which translates sequences of instructions from a target instruction set for a target processor to sequences of instructions for the host microprocessor including the steps of beginning execution of a speculative sequence of target instructions by committing state of the target processor and storing memory stores previously generated by execution at a point in the execution of instructions at which state of the target processor is known, executing the speculative sequence of host instructions until another point in the execution of target instructions at which state of the target processor is known, rolling back to last committed state of the target processor and discarding the memory stores generated by the speculative sequence of host instructions if execution fails, and beginning execution of a next sequence of target instructions if execution succeeds.Type: GrantFiled: March 9, 2010Date of Patent: January 23, 2018Assignee: Intellectual Ventures Holding 81 LLCInventors: Linus Torvalds, Robert Bedichek, Stephen Johnson
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Patent number: 8418153Abstract: A method for executing a target application on a host processor including the steps of translating each target instruction being to be executed into host instructions, storing the translated host instructions, executing the translated host instructions, responding to an exception during execution of a translated instruction by rolling back to a point in execution at which correct state of a target processor is known, and interpreting each target instruction in order from the point in execution at which correct state of a target processor is known.Type: GrantFiled: October 13, 2009Date of Patent: April 9, 2013Inventors: Robert Bedichek, Linus Torvalds, David Keppel
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Publication number: 20120036502Abstract: In one embodiment, after translating a plurality of target instructions from a target memory location into a plurality of host instructions, a write operation to a target memory portion which includes said target memory location is detected. In response to the detecting, a copy of the target instructions is stored in a host memory. In response to an attempt to execute the host instructions, the copy is compared with a plurality of current target instructions presently stored in the target memory location. Further, in response to a mismatch based on the comparison, the host instructions are disabled.Type: ApplicationFiled: February 4, 2011Publication date: February 9, 2012Inventors: John Banning, H. Peter Anvin, Robert Bedichek, Guillermo J. Rozas, Andrew Shaw, Linus Torvalds, Jason Wilson
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Patent number: 7904891Abstract: In one embodiment, after translating a plurality of target instructions from a target memory location into a plurality of host instructions, a write operation to a target memory portion which includes said target memory location is detected. In response to the detecting, a copy of the target instructions is stored in a host memory. In response to an attempt to execute the host instructions, the copy is compared with a plurality of current target instructions presently stored in the target memory location. Further, in response to a mismatch based on the comparison, the host instructions are disabled.Type: GrantFiled: July 22, 2008Date of Patent: March 8, 2011Inventors: John Banning, H. Peter Anvin, Robert Bedichek, Guillermo J. Rozas, Andrew Shaw, Linus Torvalds, Jason Wilson
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Publication number: 20100262955Abstract: A method for executing a target application on a host processor including the steps of translating each target instruction being to be executed into host instructions, storing the translated host instructions, executing the translated host instructions, responding to an exception during execution of a translated instruction by rolling back to a point in execution at which correct state of a target processor is known, and interpreting each target instruction in order from the point in execution at which correct state of a target processor is known.Type: ApplicationFiled: October 13, 2009Publication date: October 14, 2010Inventors: Robert Bedichek, Linus Torvalds, David Keppel
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Patent number: 7761857Abstract: A method for executing a target application on a host processor including the steps of translating each target instruction being to be executed into host instructions, storing the translated host instructions, executing the translated host instructions, responding to an exception during execution of a translated instruction by rolling back to a point in execution at which correct state of a target processor is known, and interpreting each target instruction in order from the point in execution at which correct state of a target processor is known.Type: GrantFiled: October 13, 1999Date of Patent: July 20, 2010Inventors: Robert Bedichek, Linus Torvalds, David Keppel
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Publication number: 20100169613Abstract: A method for use by a host microprocessor which translates sequences of instructions from a target instruction set for a target processor to sequences of instructions for the host microprocessor including the steps of beginning execution of a speculative sequence of target instructions by committing state of the target processor and storing memory stores previously generated by execution at a point in the execution of instructions at which state of the target processor is known, executing the speculative sequence of host instructions until another point in the execution of target instructions at which state of the target processor is known, rolling back to last committed state of the target processor and discarding the memory stores generated by the speculative sequence of host instructions if execution fails, and beginning execution of a next sequence of target instructions if execution succeeds.Type: ApplicationFiled: March 9, 2010Publication date: July 1, 2010Inventors: Linus Torvalds, Robert Bedichek, Stephen Johnson
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Patent number: 7694113Abstract: A method for use by a host microprocessor which translates sequences of instructions from a target instruction set for a target processor to sequences of instructions for the host microprocessor including the steps of beginning execution of a speculative sequence of target instructions by committing state of the target processor and storing memory stores previously generated by execution at a point in the execution of instructions at which state of the target processor is known, executing the speculative sequence of host instructions until another point in the execution of target instructions at which state of the target processor is known, rolling back to last committed state of the target processor and discarding the memory stores generated by the speculative sequence of host instructions if execution fails, and beginning execution of a next sequence of target instructions if execution succeeds.Type: GrantFiled: February 28, 2005Date of Patent: April 6, 2010Inventors: Linus Torvalds, Robert Bedichek, Stephen Johnson
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Patent number: 7617088Abstract: In a computer which translates instructions from a target instruction set to a host instruction set, a method for determining validity of a translation of a target instruction linked to an earlier translation including the steps of testing a memory address of a target instruction to be executed against a copy of the memory address of the target instruction from which a translation of the target instruction was made, executing the translation if the addresses compare, and generating an exception if the addresses do not compare.Type: GrantFiled: January 18, 2005Date of Patent: November 10, 2009Inventors: Robert Bedichek, David Keppel, John Banning
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Patent number: 7404181Abstract: A method of translating instructions from a target instruction set to a host instruction set. In one embodiment, a plurality of first target instructions is translated into a plurality of first host instructions. After the translation, it is determined whether the plurality of first target instructions has changed. A copy of a second plurality of target instructions is stored and compared with the plurality of first target instructions if the determining slows the operation of the computer system. After comparing, the plurality of first host instructions is invalidated if there is a mismatch. According to one embodiment, the storing, the comparing and the invaliding is initiated when the determining indicates that a page contains at least one change to the plurality of first target instructions. In one embodiment, the determining is by examining a bit indicator associated with a memory location of the plurality of first target instructions.Type: GrantFiled: August 21, 2006Date of Patent: July 22, 2008Assignee: Transmeta CorporationInventors: John Banning, H. Peter Anvin, Robert Bedichek, Guillermo J. Rozas, Andrew Shaw, Linus Torvalds, Jason Wilson
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Patent number: 7096460Abstract: In a computer system that translates target instructions from a target instruction set into host instructions from a host instruction set, a method for checking a sequence of target instructions for changes. The method includes testing whether the target instructions at a memory location have changed subsequent to the translating by examining a bit indicator associated with the memory location and determining whether the testing is slowing the operation of the computer system. If the testing is slowing the operation of the computer system, a checking process initiated, which includes storing a copy of the sequence of target instructions and comparing the copy with the sequence of target instructions.Type: GrantFiled: June 16, 2003Date of Patent: August 22, 2006Assignee: Transmeta CorporationInventors: John Banning, H. Peter Anvin, Robert Bedichek, Guillermo J. Rozas, Andrew Shaw, Linus Torvalds, Jason Wilson
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Patent number: 6990658Abstract: A method for use by a host microprocessor which translates sequences of instructions from a target instruction set for a target processor to sequences of instructions for the host microprocessor including the steps of beginning execution of a speculative sequence of target instructions by committing state of the target processor and storing memory stores previously generated by execution at a point in the execution of instructions at which state of the target processor is known, executing the speculative sequence of host instructions until another point in the execution of target instructions at which state of the target processor is known, rolling back to last committed state of the target processor and discarding the memory stores generated by the speculative sequence of host instructions if execution fails, and beginning execution of a next sequence of target instructions if execution succeeds.Type: GrantFiled: October 13, 1999Date of Patent: January 24, 2006Assignee: Transmeta CorporationInventors: Linus Torvalds, Robert Bedichek, Stephen Johnson
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Patent number: 6871342Abstract: A method for use by a host microprocessor which translates sequences of instructions from a target instruction set for a target processor to sequences of instructions for the host microprocessor including the steps of beginning execution of a speculative sequence of target instructions by committing state of the target processor and storing memory stores previously generated by execution at a point in the execution of instructions at which state of the target processor is known, executing the speculative sequence of host instructions until another point in the execution of target instructions at which state of the target processor is known, rolling back to last committed state of the target processor and discarding the memory stores generated by the speculative sequence of host instructions if execution fails, and beginning execution of a next sequence of target instructions if execution succeeds.Type: GrantFiled: October 13, 1999Date of Patent: March 22, 2005Assignee: Transmeta CorporationInventors: Linus Torvalds, Robert Bedichek, Stephen Johnson
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Patent number: 6845353Abstract: In a computer which translates instructions from a target instruction set to a host instruction set, a method for determining validity of a translation of a target instruction linked to an earlier translation including the steps of testing a memory address of a target instruction to be executed against a copy of the memory address of the target instruction from which a translation of the target instruction was made, executing the translation if the addresses compare, and generating an exception if the addresses do not compare.Type: GrantFiled: December 23, 1999Date of Patent: January 18, 2005Assignee: Transmeta CorporationInventors: Robert Bedichek, David Keppel, John Banning
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Patent number: 6594821Abstract: A method for maintaining consistency between translated host instructions and target instructions from which the host instructions have been translated including the steps of maintaining a copy of a target instruction for which a translated host instruction have been made, comparing the copy of the target instruction with a target instruction at a memory address at which the target instruction from which the copy was made was stored when translated, disabling the translated host instruction if the copy of the target instruction is not the same as the target instruction at the memory address, and executing the translated host instruction if the copy of the target instruction is the same as the target instruction at the memory address.Type: GrantFiled: March 30, 2000Date of Patent: July 15, 2003Assignee: Transmeta CorporationInventors: John Banning, H. Peter Anvin, Robert Bedichek, Guillermo J. Rozas, Andrew Shaw, Linus Torvalds, Jason Wilson
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Patent number: 6415379Abstract: A method of maintaining translation context for instructions translated from instructions designed for a target microprocessor to run on a host microprocessor including storing translation context related to each translated host instruction, indicating a translation context for host instructions presently being executed by the host processor, comparing translation context stored for a next host instruction with the translation context for a host instruction presently being executed, executing the next host instruction if the translation context of the next host instruction and the presently executing host instruction compare, and searching for an instruction with translation context which compares to the translation context of the host instruction presently executing if the translation context of the next host instruction and the presently executing host instruction do not compare.Type: GrantFiled: October 13, 1999Date of Patent: July 2, 2002Assignee: Transmeta CorporationInventors: David Keppel, Robert Cmelik, Robert Bedichek
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Patent number: 5905855Abstract: A computer implemented process for detecting errors in computer systems including the steps of executing sequences of instructions of a software program on each of a reference system and a test system, detecting and recording state of the reference system and the test system at comparable points in the execution of the program, and comparing the detected state of the reference system and the test system at selectable comparable points in the sequence of instructions including the end of the sequence of instructions. In a particular embodiment, the execution of portions of the sequence of instructions between selectable comparable points on each of the reference system and the test system is automatically replayed if a difference in compared state of the systems is detected.Type: GrantFiled: February 28, 1997Date of Patent: May 18, 1999Assignee: Transmeta CorporationInventors: Alex Klaiber, Robert Bedichek, David Keppel