Abstract: The Data Throughput Tester (“DTT”) provides efficient and reliable methods to characterize the performance capabilities of electronic data systems. Embodiments of the DTT may allow test organizations to find the throughput limitations of a data system under test to the nearest whole packet in both an efficient and reliable manner. Embodiments of the DTT may allow determination of the throughput of a data system under test under the requirement that data output obtained from the data system is identical to the data input provided to the data system. Further embodiments of the DTT may allow determination of the throughput of a data system under test under the condition that specific performance characteristics of the data system under test satisfy pre-defined benchmark parameters.

Abstract: The Data Throughput Tester (“DTT”) provides efficient and reliable methods to characterize the performance capabilities of electronic data systems. Embodiments of the DTT may allow test organizations to find the throughput limitations of a data system under test to the nearest whole packet in both an efficient and reliable manner. Embodiments of the DTT may allow determination of the throughput of a data system under test under the requirement that data output obtained from the data system is identical to the data input provided to the data system. Further embodiments of the DTT may allow determination of the throughput of a data system under test under the condition that specific performance characteristics of the data system under test satisfy pre-defined benchmark parameters.

Abstract: An address conversion unit for a multiprocessor system including a common memory, and in which at least one processor includes a private memory, with the private memory and common memory having separate and distinct memory spaces. The conversion unit converts addresses between private addresses that are used within the processor itself and addresses that are used to retrieve contents of locations in common memory.

Abstract: A control arrangement for coordinating operations of multiple processors in a multiprocessor system in response to a command. Each command is associated with a route comprising a sequence of route vectors, each identifying an operation to be performed to execute the command, as well as the process, or station, to execute the route vector. In response to the receipt of a command, a control block is generated identifying the first route vector in the route associated with the command. Each station has a work queue containing control blocks, which the station retrieves and processes sequentially. The control block is first sent to the work queue of the station to perform the first operation. When the station gets to the control block, it performs the operation required by the route vector, modifies the control block to identify the next route vector in the sequence, and transfers the control block to the work queue of the station to perform the operation required by the next route vector in the route.