Abstract: A device is described, including a first diffusion region having a first terminal, a second diffusion region having a second terminal, and a channel region disposed between the first diffusion region and the second diffusion region. Further, the first terminal and the second terminal are offset to enable a non-Manhattan current flow. A system is also described, including the previously described device and a second transistor. The pathway for the flow of the majority of the current carriers in the device defines a first direction. The second transistor also has at least two terminals, and a pathway for a majority of current carriers between the two terminals defines a second direction. The angle between the first direction and the second direction is nonzero and acute.

Abstract: One embodiment of the present invention provides a system for detecting light which is incident to a first semiconductor die. During operation, the system receives light at a photo-detector on the first semiconductor die, wherein associated circuitry converts the received light into a current. In doing so, the associated circuitry biases a gate voltage of an integrating transistor to be close to a threshold voltage of the integrating transistor, and applies the current from the photo-detector to the gate of the integrating transistor so that the current causes a charge to collect at the gate of the integrating transistor. This charge builds up and causes the integrating transistor to switch, thereby indicating that light has been received by the photo-detector.

Abstract: A method and apparatus for providing equalization for a communication channel is provided. The invention uses edge transition samples, such as those obtained for phase detection in a phase locked loop (PLL) circuit, to determine the amount of equalization to be applied to signals received from a communication channel. By monitoring run lengths of consecutive identical bits received from the communication channel, the invention provides equalization for various frequency components present in the receive signal. One embodiment of the invention subtracts a weighted RC-filtered version of the receive signal from the unfiltered receive signal to provide an equalized receive signal. In this embodiment, a control circuit that monitors the received run lengths and edge transition information adjusts the resistance of the RC filter to adapt the equalization to the data being received and the potentially time varying conditions for the communication channel.

Abstract: The present invention is a frequency controlled bias generator for stabilizing clock generation circuits. The invention includes a Bias VCO and a clock feedback circuit along with a Phase Frequency Detector for tracking and correcting variations in the frequencies of a High Speed VCO. According to the invention, variations in the frequency of the High Speed VCO are tracked and adjusted across process, temperature, and voltage variations. The invention compares the frequencies of an internal clock generated by Bias VCO with an external clock. When the internal clock frequency is undesirably high or low (based on undesirable variations in process, temperature, and voltage parameters), bias currents provided to the High Speed VCO and the Bias VCO are adjusted such that the frequencies of the Bias VCO and the High Speed VCO are adjusted to offset the variations in process, temperature, and voltage parameters. The bias currents provided to the Bias VCO and the High Speed VCO are matched.