Abstract: A data processing system includes a microprocessor having access to multiple levels of cache memories. The microprocessor executes a main thread compiled from a source code object. The system includes a processor for executing an assist thread also derived from the source code object. The assist thread includes memory reference instructions of the main thread and only those arithmetic instructions required to resolve the memory reference instructions. A scheduler configured to schedule the assist thread in conjunction with the corresponding execution thread is configured to execute the assist thread ahead of the execution thread by a determinable threshold such as the number of main processor cycles or the number of code instructions. The assist thread may execute in the main processor or in a dedicated assist processor that makes direct memory accesses to one of the lower level cache memory elements.

Abstract: An efficient method for selecting a minimal and statistically relevant set of SER sensitive logic devices critical to the SER robustness for a design, through identification by device type, identification nomenclature, connectivity and context. The minimal set of devices comprise the set of fault injection test points using a conventional fault injection test verification environment to establish an SER induced failure rate a logic design. The selection method affords a design independent means to evaluate any design regardless of the origin, source language or documentation by working at the common logic device level “gate-level” netlist format for the design data. The selected set of devices is distilled from the design data by successively filtering the design through a series of heuristic rule-based device identifier computer programs that group and annotate the devices into specific database records.

Abstract: The present invention provides a computer implemented method, apparatus, and computer usable program code for compiling instructions to manage a cache system. Loop constructs are analyzed to identify data usage characteristics for cache and prefetching conditions in instructions to form identified prefetch conditions. A set of control instructions are inserted into the instructions based on the data usage characteristics and the identified prefetch conditions to form multiple modified instructions. The set of multiple modified instructions are compiled to generate code for execution to form compiled instructions. The set of control instructions in the compiled instructions form a cache management policy to control movement of data in a memory system during execution of the compiled instructions.

Abstract: A system to determine fault tolerance in an integrated circuit may include a programmable logic device carried by the integrated circuit. The system may also include a configurable memory carried by the programmable logic device to control the function and/or connection of a portion of the programmable logic device. The system may further include user logic carried by said programmable logic device and in communication with a user and/or the configurable memory. The user logic may identify corrupted data in the configurable memory based upon changing user requirements.

Abstract: A data processing system includes a microprocessor having access to multiple levels of cache memories. The microprocessor executes a main thread compiled from a source code object. The system includes a processor for executing an assist thread also derived from the source code object. The assist thread includes memory reference instructions of the main thread and only those arithmetic instructions required to resolve the memory reference instructions. A scheduler configured to schedule the assist thread in conjunction with the corresponding execution thread is configured to execute the assist thread ahead of the execution thread by a determinable threshold such as the number of main processor cycles or the number of code instructions. The assist thread may execute in the main processor or in a dedicated assist processor that makes direct memory accesses to one of the lower level cache memory elements.

Abstract: A data processing system includes a microprocessor having access to multiple levels of cache memories. The microprocessor executes a main thread compiled from a source code object. The system includes a processor for executing an assist thread also derived from the source code object. The assist thread includes memory reference instructions of the main thread and only those arithmetic instructions required to resolve the memory reference instructions. A scheduler configured to schedule the assist thread in conjunction with the corresponding execution thread is configured to execute the assist thread ahead of the execution thread by a determinable threshold such as the number of main processor cycles or the number of code instructions. The assist thread may execute in the main processor or in a dedicated assist processor that makes direct memory accesses to one of the lower level cache memory elements.

Abstract: Compressed memory systems are provided to reduce latency associated with accessing compressed memory using stratified compressed memory architectures and memory organization protocols in which a region of compressed main memory is allocated as a direct access memory (DAM) region for storing uncompressed data items. The uncompressed data items in the DAM region can be directly accessed, speculatively, to serve access requests to main memory, requiring access to compressed memory in the event of a DAM miss.

Abstract: Methods, systems, and media for reducing memory latency seen by processors by providing a measure of control over on-chip memory (OCM) management to software applications, implicitly and/or explicitly, via an operating system are contemplated. Many embodiments allow part of the OCM to be managed by software applications via an application program interface (API), and part managed by hardware. Thus, the software applications can provide guidance regarding address ranges to maintain close to the processor to reduce unnecessary latencies typically encountered when dependent upon cache controller policies. Several embodiments utilize a memory internal to the processor or on a processor node so the memory block used for this technique is referred to as OCM.

Abstract: An efficient method for selecting a minimal and statistically relevant set of SER sensitive logic devices critical to the SER robustness for a design, through identification by device type, identification nomenclature, connectivity and context. The minimal set of devices comprise the set of fault injection test points using a conventional fault injection test verification environment to establish an SER induced failure rate a logic design. The selection method affords a design independent means to evaluate any design regardless of the origin, source language or documentation by working at the common logic device level “gate-level” netlist format for the design data. The selected set of devices is distilled from the design data by successively filtering the design through a series of heuristic rule-based device identifier computer programs that group and annotate the devices into specific database records.

Abstract: A system to determine fault tolerance in an integrated circuit may include a programmable logic device carried by the integrated circuit. The system may also include a configurable memory carried by the programmable logic device to control the function and/or connection of a portion of the programmable logic device. The system may further include user logic carried by said programmable logic device and in communication with a user and/or the configurable memory. The user logic may identify corrupted data in the configurable memory based upon changing user requirements.

Abstract: A computer compressed memory system for storing and retrieving data in a processing system, includes a memory including at least one memory device for storing at least one of uncompressed data and compressed data, a compressor for encoding data blocks into smaller compressed data blocks for storage in the memory, a decompressor for reconstituting encoded data into original uncompressed data blocks, a memory controller for generating, receiving and responding to memory access requests from processing and input/output units and responsively controlling access to the memory from the compressor and the decompressor for storing and retrieving data, and a hardware priority filter associated with the memory controller for selecting specific memory access requests according to attributes and access type within prescribed rates and under specific conditions.

Abstract: Methods, systems, and media for reducing memory latency seen by processors by providing a measure of control over on-chip memory (OCM) management to software applications, implicitly and/or explicitly, via an operating system are contemplated. Many embodiments allow part of the OCM to be managed by software applications via an application program interface (API), and part managed by hardware. Thus, the software applications can provide guidance regarding address ranges to maintain close to the processor to reduce unnecessary latencies typically encountered when dependent upon cache controller policies. Several embodiments utilize a memory internal to the processor or on a processor node so the memory block used for this technique is referred to as OCM.

Abstract: Methods, systems, and media for reducing memory latency seen by processors by providing a measure of control over on-chip memory (OCM) management to software applications, implicitly and/or explicitly, via an operating system are contemplated. Many embodiments allow part of the OCM to be managed by software applications via an application program interface (API), and part managed by hardware. Thus, the software applications can provide guidance regarding address ranges to maintain close to the processor to reduce unnecessary latencies typically encountered when dependent upon cache controller policies. Several embodiments utilize a memory internal to the processor or on a processor node so the memory block used for this technique is referred to as OCM.

Abstract: Compressed memory systems are provided to reduce latency associated with accessing compressed memory using stratified compressed memory architectures and memory organization protocols in which a region of compressed main memory is allocated as a direct access memory (DAM) region for storing uncompressed data items. The uncompressed data items in the DAM region can be directly accessed, speculatively, to serve access requests to main memory, requiring access to compressed memory in the event of a DAM miss.

Abstract: An architecture, method and apparatus for a data processing system having memory compression and two common memories forming either a single unified memory, or a dual memory system capable of continuous operation in the presence of a hardware failure or redundant “duplex” computer maintenance outage, without the cost of duplicating the memory devices. A memory controller employs hardware memory compression to reduce the memory requirement by half, which compensates for the doubling of the memory needed for the redundant storage. The memory controller employs error detection and correction code that is used to detect storage subsystem failure during read accesses. Upon detection of a fault, the hardware automatically reissues the read access to a separate memory bank that is logically identical to the faulty bank.

Abstract: An architecture, method and apparatus for a data processing system having memory compression and two common memories forming either a single unified memory, or a dual memory system capable of continuous operation in the presence of a hardware failure or redundant “duplex” computer maintenance outage, without the cost of duplicating the memory devices. A memory controller employs hardware memory compression to reduce the memory requirement by half, which compensates for the doubling of the memory needed for the redundant storage. The memory controller employs error detection and correction code that is used to detect storage subsystem failure during read accesses. Upon detection of a fault, the hardware automatically reissues the read access to a separate memory bank that is logically identical to the faulty bank.

Abstract: An architecture, method and apparatus for a data processing system having memory compression and two common memories forming either a single unified memory, or a dual memory system capable of continuous operation in the presence of a hardware failure or redundant “duplex” computer maintenance outage, without the cost of duplicating the memory devices. A memory controller employs hardware memory compression to reduce the memory requirement by half, which compensates for the doubling of the memory needed for the redundant storage. The memory controller employs error detection and correction code that is used to detect storage subsystem failure during read accesses. Upon detection of a fault, the hardware automatically reissues the read access to a separate memory bank that is logically identical to the faulty bank.

Abstract: A system and method for extracting data from a protected region of memory loads at least a first part of extraction code into physical memory and, thereafter, activates a memory mapping facility that maps a real memory onto the physical memory and prevents programs from accessing a protected memory region of the physical memory. At least a second part of the extraction code is then loaded into the virtual memory utilizing the memory mapping facility. The extraction code is then executed to deactivate the memory mapping facility and to copy data from the protected memory region to a second physical memory region, such that reactivating the memory mapping facility will cause a real memory region to be mapped onto the second physical memory region.

Abstract: In a cache memory system, a mechanism enabling two logical cache lines to coexist within the same physical cache line, during line fill and replacement, thus minimizing the likelihood of stalling accesses to the cache while the line is being filled or replaced. A control mechanism governs access to the cache line and tracks which sub-cache line units contain old or new data, or are empty during the fill/replacement procedure. The control mechanism thus maintains a sub-cache line state for the purpose of permitting a processor to gain access to a portion of the cache line before it is completely filled or replaced.