Abstract: A system includes a ferroelectric random access memory (FRAM) array having one or more memory elements. A cycle controller cycles data to be fixed in a subset of the one or more memory elements by reading or writing the data a predetermined number of times to fix the data to a non-volatile stable state.

Abstract: A system includes a ferroelectric random access memory (FRAM) array having one or more memory elements. A cycle controller cycles data to be fixed in a subset of the one or more memory elements by reading or writing the data a predetermined number of times to fix the data to a non-volatile stable state.

Abstract: Disclosed embodiments relate to generating random numbers using two transistor, two capacitor (2T-2C) ferroelectric memory cells. In accordance with one disclosed embodiment, an n-bit random number can be generated by writing to a uniform data pattern to a set of n 2T-2C ferroelectric memory cells in a 1T-1C mode so that all ferroelectric capacitors of the n 2T-2C cells have a polarization state corresponding to the same data value (e.g., all 0's or all 1's). The n 2T-2C cells are then read in a 2T-2C mode, so that a random bit (a 0 or 1) is produced for each cell, resulting in an n-bit random number. The n-bit random number is stored in the n 2T-2C ferroelectric memory cells by a rewrite operation. Such random numbers are useful for many purposes, including security, such as authentication, integrity checking, and encryption, and for identification.

Abstract: A system includes a ferroelectric random access memory (FRAM) array having one or more memory elements. A cycle controller cycles data to be fixed in a subset of the one or more memory elements by reading or writing the data a predetermined number of times to fix the data to a non-volatile stable state.

Abstract: Disclosed embodiments relate to generating random numbers using two transistor, two capacitor (2T-2C) ferroelectric memory cells. In accordance with one disclosed embodiment, an n-bit random number can be generated by writing to a uniform data pattern to a set of n 2T-2C ferroelectric memory cells in a 1T-1C mode so that all ferroelectric capacitors of the n 2T-2C cells have a polarization state corresponding to the same data value (e.g., all 0's or all 1's). The n 2T-2C cells are then read in a 2T-2C mode, so that a random bit (a 0 or 1) is produced for each cell, resulting in an n-bit random number. The n-bit random number is stored in the n 2T-2C ferroelectric memory cells by a rewrite operation. Such random numbers are useful for many purposes, including security, such as authentication, integrity checking, and encryption, and for identification.

Abstract: A system includes a ferroelectric random access memory (FRAM) array having one or more memory elements. A cycle controller cycles data to be fixed in a subset of the one or more memory elements by reading or writing the data a predetermined number of times to fix the data to a non-volatile stable state.

Abstract: Disclosed embodiments relate to generating random numbers using two transistor, two capacitor (2T-2C) ferroelectric memory cells. In accordance with one disclosed embodiment, an n-bit random number can be generated by writing to a uniform data pattern to a set of n 2T-2C ferroelectric memory cells in a 1T-1C mode so that all ferroelectric capacitors of the n 2T-2C cells have a polarization state corresponding to the same data value (e.g., all 0's or all l's). The n 2T-2C cells are then read in a 2T-2C mode, so that a random bit (a 0 or 1) is produced for each cell, resulting in an n-bit random number. The n-bit random number is stored in the n 2T-2C ferroelectric memory cells by a rewrite operation. Such random numbers are useful for many purposes, including security, such as authentication, integrity checking, and encryption, and for identification.

Abstract: Disclosed embodiments relate to generating random numbers using two transistor, two capacitor (2T-2C) ferroelectric memory cells. In accordance with one disclosed embodiment, an n-bit random number can be generated by writing to a uniform data pattern to a set of n 2T-2C ferroelectric memory cells in a 1T-1C mode so that all ferroelectric capacitors of the n 2T-2C cells have a polarization state corresponding to the same data value (e.g., all 0's or all l's). The n 2T-2C cells are then read in a 2T-2C mode, so that a random bit (a 0 or 1) is produced for each cell, resulting in an n-bit random number. The n-bit random number is stored in the n 2T-2C ferroelectric memory cells by a rewrite operation. Such random numbers are useful for many purposes, including security, such as authentication, integrity checking, and encryption, and for identification.

Abstract: A system includes a ferroelectric random access memory (FRAM) array having one or more memory elements. A cycle controller cycles data to be fixed in a subset of the one or more memory elements by reading or writing the data a predetermined number of times to fix the data to a non-volatile stable state.

Abstract: A multi-bit interlace latch includes a first and second latch that each have redundant active feedback paths to reduce the incidence of soft-errors. The first and second latches have active circuitry that includes nodes that are susceptible to radiation-induced soft errors. Active circuitry from the second latch is interlaced between active circuitry of the first latch to increase the isolation between critical nodes of the first latch. While the second latch circuit increases isolation between critical nodes of the first latch, the first latch may also benefit the second latch by increasing the isolation between critical nodes of the first latch as well.

Abstract: The present invention provides, in one aspect, a method of designing an integrated circuit. In this particular aspect, the method comprises reducing soft error risk in an integrated circuit by locating a structure, relative to a node of the integrated circuit to reduce a linear energy transfer associated with a sub-atomic particle, into the node, such that the linear energy transfer does not exceed a threshold value associated with the integrated circuit.

Abstract: The present invention provides, in one aspect, a method of designing an integrated circuit. In this particular aspect, the method comprises reducing soft error risk in an integrated circuit by locating a structure, relative to a node of the integrated circuit to reduce a linear energy transfer associated with a sub-atomic particle, into the node, such that the linear energy transfer does not exceed a threshold value associated with the integrated circuit.

Abstract: A memory circuit and method for reducing the effects of memory imprinting is disclosed. The circuit includes a plurality 1500 of nonvolatile memory cells for storing data. A control terminal 1520 is arranged to receive a control signal INV. A data circuit 1510, 1512 is coupled to the control terminal and arranged to invert the data in the nonvolatile memory cells in response to the control signal. Repeated inversion of the data state of the nonvolatile memory cells reduces the effects of memory imprinting.

Abstract: A method for making a CMOS device includes: forming a PMOS region 60 of a first conductivity type; forming an NMOS region 62 of a second conductivity type adjacent the PMOS region 60; forming an insulating layer 64 and 66 over the PMOS region 60 and the NMOS region 62 such that the insulating layer is thinner over the PMOS region than over the NMOS region; forming a common gate 48 over the insulating layer 64 and 66; forming PMOS source/drain regions 40 and 42 of the second conductivity type in the PMOS region 60 and aligned to the common gate 48; and forming NMOS source/drain regions 44 and 46 of the first conductivity type in the NMOS region 62 and aligned to the common gate 48.

Abstract: Reduced soft errors in charge-sensitive circuit elements such as volatile memory cells 200 occur by using boron-11 to the exclusion of boron-10 or essentially free of boron-10 in borosilicate glass 230, 240 deposited on the substrate 206 directly over the arrays of memory cells. Boron-10 exhibits a high likelihood of fission to release a 1.47 MeV alpha particle upon capture of a naturally occurring cosmic ray neutron. This capture occurs frequently in boron-10 because of its high neutron capture cross-section. Boron-11 does not fission.

Abstract: Reduced soft errors in charge-sensitive circuit elements such as volatile memory cells 200 occur by using boron-11 to the exclusion of boron-10 or essentially free of boron-10 in borosilicate glass 230, 240 deposited on the substrate 206 directly over the arrays of memory cells. Boron-10 exhibits a high likelihood of fission to release a 1.47 MeV alpha particle upon capture of a naturally occurring cosmic ray neutron. This capture occurs frequently in boron-10 because of its high neutron capture cross-section. Boron-11 does not fission.