Abstract: A SCSI initiator, repeater, or device is provided that stretches an initial assertion of the REQ# or ACK# clock signals on the SCSI bus after a period of inactivity on the SCSI data lines. This discharges built up charge allowing greater signal integrity on ensuing clocks.

Abstract: A parallel reactor system and method therefor are disclosed. The parallel reactor is used to synthesize and/or screen multiple compounds or materials at the same time. Preferably, open-ended reactor vessels in the parallel reactor allow the pressure therein to remain substantially constant. An injection system delivers a specific mixture of gas to each reactor vessel. Preferably, the gas mixtures are delivered at substantially the same flow rate for some or all reactor vessels.

Abstract: A bridge logic unit provides an interface between a microprocessor coupled to a processor bus, a main memory coupled to memory bus, and a peripheral device coupled to a peripheral bus, such as a PCI bus. To maintain coherency, the bridge logic unit disables write posting in certain specific situations, and flushes posted write transactions before allowing certain read requests to be serviced. More specifically, in one embodiment when a PCI device performs a read to main memory, which may be implemented within the bridge as delayed read, the bus bridge blocks CPU to PCI transactions and flushes any posted CPU to PCI transactions pending in the bridge. The bus bridge enables CPU to PCI posting after the pending CPU to PCI transactions have been flushed and after the snoop phase of a snoop cycle corresponding to the memory read operation completes.

Abstract: A computer system includes a South bridge logic device that monitors the FLUSHREQ signal and masks that signal when the CPU transitions the computer to a low power mode of operation. Once masked, the FLUSHREQ cannot be asserted to the North bridge and the conflict between attempts by the CPU and an ISA device to run cycles on the PCI bus is avoided. The South bridge also masks all requests to run cycles on the PCI bus that are not originated by the CPU. The South bridge includes a programmable control register and a PCI arbiter. When a control bit is set in the register, the PCI arbiter waits for FLUSHREQ to be deasserted and then masks FLUSHREQ. The PCI arbiter preferably also disables PCI arbitration by masking all non-CPU. Only the CPU can run PCI cycles when the non-CPU requests are masked. The programmable control register also includes a masking status bit that is set when both the FLUSHREQ and non-CPU request signals are masked by a request mask state machine.

Abstract: A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a memory page, and feature flags that may be used to customize the associated memory page.

Abstract: A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a page of graphics data in memory, and feature flags that may be used to customize the associated page. One of the feature flags is used as a Present Bit for a corresponding memory page.

Abstract: A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. A plurality of AGP memory-mapped status and control registers are stored in the computer system memory, and are used for status and control of AGP functions in the computer system.

Abstract: A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a page of graphics data in the computer system physical memory, and feature flags that may be used to customize the associated page of graphics data.

Abstract: A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. Contiguous virtual memory address space must be allocated for the AGP device within the addressable memory space of the computer system, typically 4 gigabytes using 32 bit addressing.

Abstract: A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a page of graphics data in memory, and feature flags that may be used to customize the associated page.

Abstract: A distributed direct memory access (DMA) architecture where DMA controllers are modified to create isolated DMA channels. Each isolated channel includes its own set of uniquely addressable registers which provide functional compatibility with conventional DMA controllers. A DMA master interacts compatibly with the computer system and transparently communicates special cycles to the isolated DMA channels to cause the distributed DMA architecture to appear as the DMA controllers. The DMA master spawns special cycles to the isolated channels for sharing common write data with multiple channels and merging read data into a single DMA controller compatible register. Channel 4 cascading is also handled via tracking registers and special cycles to maintain disable and masking functionality of channel 4 as it effects channels 0-3.

Abstract: A non-intrusive optical transmission liquid monitoring system that detects bubbles in a transparent liquid flowing through a transparent tubing. The system dynamically compensates for changes in optical transmission efficiency of the monitored liquid and distinguishes between the transition from liquid to air and air to liquid. A system comprising a light transmitter and a light sensitive receiver secured on opposite sides of a transparent tubing. The output of the receiver is fed into a self-referencing and drift compensation circuit. The integrated output is connected to circuitry sensitive to a change in the integrated output and triggers one of two possible alarms to indicate a detected transition from liquid to air, or air to liquid.

Abstract: An apparatus for controlling a heating element for heating a substance in accordance with a maximum power which is to be applied to the heating element and in accordance with a selected temperature to which the substance is to be heated is used in combination with a temperature sensing probe for sensing the temperature of the substance heated by the heating element. The apparatus includes first circuitry for generating a first control signal which is a function of the difference between the selected temperature and the sensed temperature and second circuitry for generating a second control signal which is a function of the maximum power.