Abstract: A multi-signal multi-coder transcoder is disclosed for communications systems that can be fabricated less expensively than embodiments in the prior art and without requiring significant changes to the signal source and destination devices. An illustrative embodiment preferably comprises an input lead, an output lead, an input switch, an output switch, a pool of N processing elements, which are configured to perform a first coding technique and a pool of M processing elements, which are configured to perform a second coding technique, or possibly both techniques. When the input lead carries a plurality of multiplexed signals, each of which is to be transcoded in accordance with one of the two coding techniques, the input switch segregates and routes the incoming signals to an appropriate processing element. While a processing element is preferably configured to perform only one coding technique, each is preferably capable of transcoding multiple signals concurrently in accordance with that technique.

Abstract: A processor specially adapted for use as a coprocessor. The processor is implemented as a microprocessor. The adaptations include the following: The microprocessor has a master-slave pin which receives an input which determines whether the microprocessor operates as a bus master or a bus slave. Certain output pins have three-state bus drivers which employ feedback to ensure that a signal on a line being even by the driver has gone inactive before the driver is turned off. Instructions executed by the microprocessor permit specification of portions of the internal registers as sources and destinations and specification of the size of an ALU operation, permitting easy operation on data ranging from bytes through 24-bit pointers. Instructions are executed in an instruction pipeline and a separate I/O instruction pipeline.

Abstract: A processor specially adapted for use as a coprocessor. The processor is implemented as a microprocessor. The adaptations include the following: The microprocessor has a master-slave pin which receives an input which determines whether the microprocessor operates as a bus master or a bus slave. Certain output pins have three-state bus drivers which employ feedback to ensure that a signal on a line being driven by the driver has gone inactive before the driver is turned off. Instructions executed by the microprocessor permit specification of portions of the internal registers as sources and destinations and specification of the size of an ALU operation, permitting easy operation on data ranging from bytes through 24-bit pointers. Instructions are executed in an instruction pipeline and a separate I/O instruction pipeline.

Abstract: A processor which is specially adapted for use as a coprocessor. The processor is implemented as a microprocessor. The adaptations include the following: The microprocessor has a master-slave pin which receives an input which determines whether the microprocessor operates as a bus master or a bus slave. Certain output pins have three-state bus drivers which employ feedback to ensure that a signal on a line being driven by the driver has gone inactive before the driver is turned off. Instructions executed by the microprocessor permit specification of portions of the internal registers as sources and destinations and specification of the size of an ALU operation, permitting easy operation on data ranging from bytes through 24-bit pointers. Instructions are executed in an instruction pipeline and a separate I/O instruction pipeline.

Abstract: A processor specially adapted for use as a coprocessor. The processor is implemented as a microprocessor. The adaptations include the following: The microprocessor has a master-slave pin which receives an input which determines whether the microprocessor operates as a bus master or a bus slave. Certain output pins have three-state bus drivers which employ feedback to ensure that a signal on a line being driven by the driver has gone inactive before the driver is turned off. Instructions executed by the microprocessor permit specification of portions of the internal registers as sources and destinations and specification of the size of an ALU operation, permitting easy operation on data ranging from bytes through 24-bit pointers. Instructions are executed in an instruction pipeline and a separate I/O instruction pipeline.

Abstract: A processor specially adapted for use as a coprocessor The processor is implemented as a microprocessor. The adaptations include the following: The microprocessor has a master-slave pin which receives an input which determines whether the microprocessor operates as a bus master or a bus slave. Certain outputs pins have three-state bus drivers which employ feedback to ensure that a signal on a line being driven by the driver has gone inactive before the driver is turned off. Instructions executed by the microprocessor permit specification of portions of the internal registers as sources and destinations and specification of the size of an ALU operation, permitting easy operation on data ranging from bytes through 24-bit pointers. Instructions are executed in an instruction pipeline and a separate I/O instruction pipeline.

Abstract: A synchronous protocol data formatter handles all 24-32 channels of a so-called primary rate version of a digital multiplexed interface or ISDN Primary Rates Interface for a communication system. The formatter relieves the host computer of the local area network of some highly specialized tasks, and, at the same time, provides the following augmented capabilities, which exceed those required by the C.C.I.T.T. standard, I.431:1. dynamic channel bandwidth allocation can assign arbitrary (even non-adjacent) time slots to create a super channel;2. a circular interrupt-queue in a shared memory enables the formatter and the host computer of the local area network to interact efficiently in updating and responding to changing conditions; and3. cyclical redundancy codes can be used on a more flexible basis than theretofore, e.g., can be generated upon only address and control fields for digitized voice signals, or, in a relay mode, can substitute an existing cyclical redundancy code to guard against memory errors.

Abstract: A random number generator (RNG) uses an edge-triggered D-type flip-flop with a high frequency square wave having an approximately 50 percent duty cycle connected to a data input terminal and a low frequency square wave connected to a clock input terminal, a five-state counter, five two-input AND gates, five exclusive-OR gates, and five shift registers. An essentially truly random number is generated at the RNG output terminals. Probability biases due to both variations in the 50 percent duty cycle of the data waveform and small amounts of cycle-to-cycle jitter of the clock waveform are effectively removed.