Abstract: A digital data system employs multiple error protection mechanisms on messages that pass along a link interconnect fabric from one node or device to another node or device. The nodes may be end points (such as processor or storage units), or may be intermediate devices or branch points (such as routers or switches in the interconnect fabric). The interconnect fabric comprises a set of one or more routers, switches, electrical, optical, electroptical or other links along which messages are passed. Messages are packets having a defined format including, e.g., a header portion, typically with source and target addresses, and codes indicating message-type or other information, followed by one or more data or other fields. A first node (“sending” node) of a digital data system as described sends a data transmission comprising one or more message packets to a second node (“receiving” node) over a link of a fabric as described above.

Abstract: A digital data system comprises a plurality of links for passing messages between nodes, which may be end points such as memory or processing units, or intermediate or branch points such as routers or other devices in the system. A link level flow control is implemented by control symbols passed between adjacent nodes on a link to efficiently regulate message burden on the link. The control symbols may be embedded within in a message packet to quickly effect control on a link—such as reducing data flow, requesting retransmission of corrupted data, or other intervention—without disruption of the ongoing packet reception. A control symbol may be recognized within the packet by a flag bit, a marker such as a transition in a signal, or a combination of characteristics. The control symbol may be a short word, having a control action identifier code at defined bit positions to indicate the desired link-level control function.

Abstract: A data communication system (10) has a plurality of devices (12, 14, 17) which communicate by transmitting information packets having order tags which are processed by an input unit (60) and an output unit (30) in each device. A packet is sent from a transmitting device to a receiving device having an ordering tag wherein both devices are initially order synchronized by starting with the same ordering tag value. Packet transmissions are forced to occur in an order which follows a predetermined ordering of order values which the ordering tags can have. If the receiving device does not receive a packet having the correct order tag value or if a transmission error is detected, the receiving device tells the transmitting device to resend the packet. Any subsequent outstanding transmissions are discarded. Packet ordering and verification occurs at each device-to-device connection.

Abstract: A multi-processing system (50) utilizes an interconnect fabric (59) for coupling endpoint devices (52, 54, 56, 66, 67). Bus control functions are managed in a method which is bus protocol independent. Each of the endpoint devices and the fabric function by specific rules to transfer data having a priority. Within the interconnect, higher priority data transfers take precedence of servicing, and for equal priority data the data is serviced first-in, first-out. Requests of endpoint devices that require a response can not be sent at the highest priority. Endpoint devices may not allow the acceptance of data to be contingent on outputting data of equal or lesser priority than the priority of the incoming data. Transaction priority, ordering and deadlocks are efficiently handled without the interconnect fabric needing to implement a set of bus protocol rules. Within the endpoint devices, additional rules related to ordering may be implemented.

Abstract: A data communication system (10) has a plurality of devices (12,14,17) which communicate by transmitting information packets having order tags which are processed by an input unit (60) and an output unit (30) in each device. A packet is sent from a transmitting device to a receiving device having an ordering tag wherein both devices are initially order synchronized by starting with the same ordering tag value. Packet transmissions are forced to occur in an order which follows a predetermined ordering of order values which the ordering tags can have. If the receiving device does not receive a packet having the correct order tag value or if a transmission error is detected, the receiving device tells the transmitting device to resend the packet. Any subsequent outstanding transmissions are discarded. Packet ordering and verification occurs at each device-to-device connection.

Abstract: A multi-processing system (50) utilizes an interconnect fabric (59) for coupling endpoint devices (52, 54, 56, 66, 67). Bus control functions are managed in a method which is bus protocol independent. Each of the endpoint devices and the fabric function by specific rules to transfer data having a priority. Within the interconnect, higher priority data transfers take precedence of servicing, and for equal priority data the data is serviced first-in, first-out. Requests of endpoint devices that require a response can not be sent at the highest priority. Endpoint devices may not allow the acceptance of data to be contingent on outputting data of equal or lesser priority than the priority of the incoming data. Transaction priority, ordering and deadlocks are efficiently handled without the interconnect fabric needing to implement a set of bus protocol rules. Within the endpoint devices, additional rules related to ordering may be implemented.

Abstract: A multicomputer is shown made up of a crossbar network to which are connected processing nodes and I/O interface nodes. The processing nodes include crossbar interface circuits that provide routing signals in local registers so that a local processor can access memory in remote processing nodes. The crossbars include circuits to establish communication paths through the crossbar networks in response to the routing signals, so that a local processor has direct access to remote memory, which is mapped into local address space. The routing signal can have a broadcast mode and can establish priority for the signal. Under some circumstances the crossbar circuit can choose between alternative paths through a crossbar. Arbitrary sized and shaped networks of crossbars can be readily implemented, and the direct memory burst transactions allow very high speed performance.