Abstract: Multilayer circuit boards include compensator networks configured in one or more conductor layers. A signal trace is configured in one or more layers to transmit an electrical signal from an input to an output and the compensator network is situated at at least one location on the trace to provide compensation for frequency dependent signal propagation losses or distortions such as those due to dielectric loss. In one example, the compensator includes a high frequency path provided by a series capacitance formed by conductor layers that include interleaved digits. Transmitters that include such compensators provide predistorted signals that can be matched or otherwise associated with anticipated propagation losses and distortions. Methods of evaluating dielectric losses include propagating electrical signals through such compensators and along a trace defined with respect to a dielectric under test and determining an associated compensation.

Abstract: Multilayer circuit boards include compensator networks configured in one or more conductor layers. A signal trace is configured in one or more layers to transmit an electrical signal from an input to an output and the compensator network is situated at at least one location on the trace to provide compensation for frequency dependent signal propagation losses or distortions such as those due to dielectric loss. In one example, the compensator includes a high frequency path provided by a series capacitance formed by conductor layers that include interleaved digits. Transmitters that include such compensators provide predistorted signals that can be matched or otherwise associated with anticipated propagation losses and distortions. Methods of evaluating dielectric losses include propagating electrical signals through such compensators and along a trace defined with respect to a dielectric under test and determining an associated compensation.

Abstract: A method and apparatus for image processing provides a memory having a plurality of individual parallel buffers constructed from random access memories (RAMs) for storing data related to a group of image pixels. The buffers each store a parallel, identical version of the image data so that an image processor can access data related to a given pixel in the overall data from each buffer simultaneously. An address expander for the buffer rows and buffer columns is used to convert a row and column address of a selected “central” pixel into a plurality of related pixel data addresses offset at predetermined distances from the selected pixel data's address. In this manner, the address expanders enable a group of related pixels, each in a different parallel buffer, to be accessed simultaneously, without requiring the processor to be interconnected with all of the buffers. This substantially reduces the complexity of processor interconnection design, while substantially enhancing processor speed.

Abstract: A method and apparatus for accessing image pixel data in a plurality of parallel random access memories (RAMs) includes providing the RAMs so that they are arranged in pairs that each include an even RAM and an odd RAM. Each of the pairs includes an identical copy of the image pixel data stored at identical addresses in each of the RAMs relative to each other. An image processor receives image pixel data from the RAMs over multi-bit data lines. and addresses rows and columns of the pairs so that alternating columns of image pixel data corresponding to alternating pixel columns in an acquired image are stored in an alternating manner in each of an even RAM and an odd RAM. In other words, pixel data of alternating odd pixel columns are stored in succeeding columns in the odd RAM and pixel data of all even pixel columns are stored in succeeding columns in the even RAM.

Abstract: The invention provides methods and systems for forming and image from a stream of non-interleaved image date, e.g., a stream of non-contiguous rows of pixels. Such a system includes a memory, in which the image is to be formed (and stored), and a controller, for initiating memory transfers that move rows of pixels from the stream to their (the rows') respective locations in memory. The controller initiates those transfers such that (i) the rows of pixels are transferred to the memory in the order in which they are received from the stream, and (ii) each row of pixels is transferred directly to the location in memory corresponding to that row's respective position in the image.

Abstract: A method and apparatus for addressing a parallel image processing memory provides a plurality of random access memories arranged in an array in a set of array rows and array columns. Each of the memories has addresses for storing image pixel data that are arranged identically to each other. Each of the random access memories stores the group of image pixel data at the identical addresses. The entire group of image pixel data is stored in each of the plurality of random access memories. The random access memories can be constructed from a plurality of individual random access memory structures that are joined as a single memory storage unit, or buffer that enables one image pixel data to be addressed in each addressing cycle. An image processor generates address values for accessing the group of image pixel data over a plurality of address lines interconnected with respective of the plurality of buffers. The image processor manipulates the group of image pixel data.