Abstract: A system and method for rapidly transferring large amounts of small-sized data to non-sequential addresses in an instumentation system. According to a preferred embodiment, a host computer includes a plurality of test vectors stored in memory which control the operation of attached instruments. The host processor generates a block of address/data pairs in response to the test vectors, with each pair containing data and a destination address. This block is stored in memory and the address of the block is provided to a random write engine. The random write engine then distributes the data to the respective instruments at the proper addresses with minimal processor invention. Therefore, large amounts of small-sized data may be rapidly transferred to non-sequential addresses without burdening the processor.

Abstract: An IEEE 488 interface couples a microprocessor to one or more devices that are connected to an IEEE 488 bus. Message transmission speed is improved by overlapping a portion of the T1 bus settling time with the microprocessor's write pulse, when it is known that the data on the microprocessor's bus is valid for a predefined period of time before the write pulse's trailing edge. Improved handshake synchronization is achieved by generating an interrupt signal to notify the microprocessor that the last byte of an incoming message has been received. The terminal count signal generated by the microprocessor's DMA controller is used to detect the end of multiple byte messages sent by the microprocessor. The interface automatically generates an EOI signal on the IEEE 488 bus when the last byte of the message is asserted on the IEEE 488 bus data lines. This greatly simplifies the transmission of multiple byte messages by the microprocessor compared with the protocol used by prior art interfaces.

Abstract: An IEEE 488 interface couples a microprocessor to one or more devices that are connected to an IEEE 488 bus. Message transmission speed is improved by overlapping a portion of the T1 bus settling time with the microprocessor's write pulse, when it is known that the data on the microprocessor's bus is valid for a predefined period of time before the write pulse's trailing edge. Improved handshake synchronization is achieved by generating an interrupt signal to notify the microprocessor that the last byte of an incoming message has been received. The terminal count signal generated by the microprocessor's DMA controller is used to detect the end of multiple byte messages sent by the microprocessor. The interface automatically generates an EOI signal on the IEEE 488 bus when the last byte of the message is asserted on the IEEE 488 bus data lines. This greatly simplifies the transmission of multiple byte messages by the microprocessor compared with the protocol used by prior art interfaces.