Abstract: A method of responding to an attempt to write a memory address including a target instruction which has been translated to a host instruction for execution by a host processor including the steps of marking a memory address including a target instruction which has been translated to a host instruction, detecting a memory address which has been marked when an attempt is made to write to the memory address, and responding to the detection of a memory address which has been marked by protecting a target instruction at the memory address until it has been assured that translations associated with the memory address will not be utilized before being updated.

Abstract: A process which automatically inserts commands that test for and raise exceptions indicating floating point status exceptions into a sequence of instructions to be executed, re-ordering a pipelined instructions by moving a floating point instruction from after a branch instruction to before the branch instruction, and responds to exceptions in execution of the sequence of instructions by returning execution to a point in the sequence of instructions at which correct state is known and then executing each instruction in the sequence singly to completion so that exceptions in pipelined floating point instructions can be automatically detected and handled precisely.

Abstract: A process which automatically inserts commands that test for raised exceptions indicating floating point status exceptions into a sequence of instructions to be executed, and responds to exceptions in execution of the sequence of instructions by returning execution to a point in the sequence of instructions at which correct state is known and then executing each instructions in the sequence singly to completion so that exceptions in pipelined floating point instructions can be automatically detected.

Abstract: A process which stores an indication of a next instruction in a sequence of instructions which is to be executed whenever during execution of instructions of the sequence it is apparent that state of the process is consistent, and refers to the stored indication to determine an instruction at which to begin re-execution of the sequence after executing a fault handler initiated by an interrupt to the sequence.

Abstract: A process which stores an indication of a next instruction in a sequence of instructions which is to be executed whenever during execution of instructions of the sequence it is apparent that state of the process is consistent, and refers to the stored indication to determine an instruction at which to begin re-execution of the sequence after executing a fault handler initiated by an interrupt to the sequence.

Abstract: A method of maintaining translation context for instructions translated from instructions designed for a target microprocessor to run on a host microprocessor including storing translation context related to each translated host instruction, indicating a translation context for host instructions presently being executed by the host processor, comparing translation context stored for a next host instruction with the translation context for a host instruction presently being executed, executing the next host instruction if the translation context of the next host instruction and the presently executing host instruction compare, and searching for an instruction with translation context which compares to the translation context of the host instruction presently executing if the translation context of the next host instruction and the presently executing host instruction do not compare.

Abstract: A backward compatible addressing scheme for increasing the number of memory locations available in a computer for storing higher precision numbers. The computer system of the present invention has a processor capable of manipulating numbers having precision S, where S is a power of 2. The memory locations are specified in an instruction address field by an n-bit logical address ##EQU1## Each S-precision number is stored in a group of S memory locations accessed by an m-bit physical address ##EQU2## Each memory location is capable of storing a single precision number. Addressing logic for addressing the memory locations with the logical addresses includes alignment logic for setting:d.sub.i =0 for 0.ltoreq.i.ltoreq.(log.sub.2 S)-1,and settingd.sub.i =e.sub.i for log.sub.2 S.ltoreq.i.ltoreq.n-1;and extension logic for settingd.sub.i =e.sub.i-nfor n.ltoreq.i.ltoreq.m-1.

Abstract: The present invention enables a computer system to store from register files to memory, and restore from memory back to the register files, data from programs designed to operate in accordance with a first word size, as well as programs designed to operate in accordance with a second word size. This is accomplished without an increase in hardware and without requiring modification of existing software. In particular, an indication is utilized at the procedure level to designate whether a particular procedure is using words of a first or second word size. Preferably, this indication is placed in a first predetermined bit position in the stack pointer of the procedure. When a save occurs, certain contents from the register file are saved to memory along with the stack pointer. Under certain circumstances, the word size indication is moved to a second predetermined bit position within the stack pointer which is stored in a predesignated stack pointer address in the save area.

Abstract: A method and apparatus are provided for enabling a computer that is capable of running programs utilizing different address sizes to run those programs without having to modify the computer's hardware. A mask register is used to identify bits of a sum of register addresses that are valid for the program that is running. The number of valid bits in the register mask can be changed to correspond to the addressable memory size for different programs.