Patents by Inventor Robert Contolini

Robert Contolini has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7211175
    Abstract: Controlled-potential electroplating provides an effective method of electroplating metals onto the surfaces of high aspect ratio recessed features of integrated circuit devices. Methods are provided to mitigate corrosion of a metal seed layer on recessed features due to contact of the seed layer with an electrolyte solution. The potential can also be controlled to provide conformal plating over the seed layer and bottom-up filling of the recessed features. For each of these processes, a constant cathodic voltage, pulsed cathodic voltage, or ramped cathodic voltage can be used. An apparatus for controlled-potential electroplating includes a reference electrode placed near the surface to be plated and at least one cathode sense lead to measure the potential at points on the circumference of the integrated circuit structure.
    Type: Grant
    Filed: February 11, 2003
    Date of Patent: May 1, 2007
    Assignee: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, Jonathan Reid, Robert Contolini
  • Patent number: 6562204
    Abstract: Controlled-potential electroplating provides an effective method of electroplating metals onto the surfaces of high aspect ratio recessed features of integrated circuit devices. Methods are provided to mitigate corrosion of a metal seed layer on recessed features due to contact of the seed layer with an electrolyte solution. The potential can also be controlled to provide conformal plating over the seed layer and bottom-up filling of the recessed features. For each of these processes, a constant cathodic voltage, pulsed cathodic voltage, or ramped cathodic voltage can be used. An apparatus for controlled-potential electroplating includes a reference electrode placed near the surface to be plated and at least one cathode sense lead to measure the potential at points on the circumference of the integrated circuit structure.
    Type: Grant
    Filed: May 10, 2001
    Date of Patent: May 13, 2003
    Assignee: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, Jonathan Reid, Robert Contolini
  • Patent number: 6551483
    Abstract: Controlled-potential electroplating provides an effective method of electroplating metals onto the surfaces of high aspect ratio recessed features of integrated circuit devices. Methods are provided to mitigate corrosion of a metal seed layer on recessed features due to contact of the seed layer with an electrolyte solution. The potential can also be controlled to provide conformal plating over the seed layer and bottom-up filling of the recessed features. For each of these processes, a constant cathodic voltage, pulsed cathodic voltage, or ramped cathodic voltage can be used. An apparatus for controlled-potential electroplating includes a reference electrode placed near the surface to be plated and at least one cathode sense lead to measure the potential at points on the circumference of the integrated circuit structure.
    Type: Grant
    Filed: May 10, 2001
    Date of Patent: April 22, 2003
    Assignee: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, Jonathan Reid, Robert Contolini
  • Patent number: 6402923
    Abstract: An electrochemical reactor is used to electrofill damascene architecture for integrated circuits. A shield is used to screen the applied field during electroplating operations to compensate for potential drop along the radius of a wafer. The shield establishes an inverse potential drop in the electrolytic fluid to overcome the resistance of a thin film seed layer of copper on the wafer.
    Type: Grant
    Filed: March 27, 2000
    Date of Patent: June 11, 2002
    Inventors: Steven T. Mayer, Richard Hill, Alain Harrus, Evan Patton, Robert Contolini, Steve Taatjes, Jon Reid