Abstract: A computer system having reduced write latency and methods for use in computer systems for reducing write latency are provided. Processing circuitry of the computer system is configured to execute a volume filter driver (VFD) that can be switched between a fast termination (FT) mode of operations and a normal, or quiescent, mode of operations. When the processing circuitry receives input/output (IO) write requests to write data to memory while the VFD is in the FT mode of operations, the VFD causes metadata associated with received IO write requests to be written to a volume of memory while preventing actual data associated with received IO write requests from being written to the volume, thereby resulting in extremely fast FT mode operation. After the file has been written to the volume, the VFD enters the quiescent mode of operations during which the VFD passes all IO write requests to the volume.

Abstract: A method for operating a data processing system to display data related to a plurality of packets that traverse a communication link is disclosed. A copy of the packets that traverse the link is provided including a timestamp corresponding to each packet that defines a time at which the packet traversed the link. A display is generated having first and second regions. The first region includes an X-Y chart in which each packet is represented by a multi-value glyph denoting a first property related to that packet, the first property having more than two values. The second region includes a first annotation glyph for one of the packets, the first annotation glyph being located at the X-location corresponding to the timestamp for the packet. The first annotation glyph is present if that data packet has a second property.

Abstract: A method for operating a data processing system to display data related to a plurality of packets that traverse a communication link is disclosed. A copy of the packets that traverse the link is provided including a timestamp corresponding to each packet that defines a time at which the packet traversed the link. A display is generated having first and second regions. The first region includes an X-Y chart in which each packet is represented by a multi-value glyph denoting a first property related to that packet, the first property having more than two values. The second region includes a first annotation glyph for one of the packets, the first annotation glyph being located at the X-location corresponding to the timestamp for the packet. The first annotation glyph is present if that data packet has a second property.

Abstract: Methods and associated apparatus for analyzing and presenting captured state logic data including memory accesses by an intelligent I/O interface device and an attached computer system. The data analysis and display of the present invention aids an engineer in locating data corruption failures in a system. The heuristic analysis of the methods of the present invention locate and identify buffers accessed within the captured state logic data and buffer descriptors accessed within the captured state logic data despite the time dispersion thereof. The buffers and buffer descriptors located and identified within the captured state logic data are displayed on a computer display screen in a manner to more effectively assist an engineer in locating a root cause of data corruption than was possible with prior methods devoid of the analysis of the present invention.