Abstract: An electronic token has at least two conductive surfaces which form either in total or in part a crush resistant casing in which a semiconductor memory is placed. Coupled to the two conductive surfaces is a set of input logic which is used to detect whether or not the first conductive surface is coupled to a device in which a first voltage or a second voltage is present and in which data can be stored in the semiconductor memory accordingly. Output logic is also provided so as to selectively poll the first conductive surface of said casing towards the second voltage with the output logic being electronically coupled to the semiconductor memory so that data may be retrieved from the stored memory. The stored information may be used for controlling access to items, for example as a lock. It may further be used as an inventory control device, postage control device, currency device for the sale of goods.

Abstract: A memory controller for supplying backup battery power when a main power supply voltage drops together with programmable plus power fail write protection. The controller includes supravoltage induced sleep mode operation, MOS switching between backup batteries during backup operation based on battery voltage levels and discharge circuitry for battery disposal.

Abstract: An integrated circuit memory which includes at least some RAM/ROM hybrid columns. The RAM/ROM hybrid cells operate as normal SRAM cells forever, unless and until they are programmed to operate as ROM cells. Thus users who need the extra security permitted by ROM encoding can have this capability, while users who do not need ROM encoding can use off-the-shelf parts as RAM only.

Abstract: An system containing an integrated circuit having two separate potentiometers combined on a single substrate; each potentiometer having three separate output terminals, two being connected to the ends of a resistor string, and the third being a "wiper" terminal electrically connected to a point within the length of the resistor string. All three terminals of each potentiometer electrically float with respect to the other pins of the integrated circuit. Control logic is used to select the point in the resistor string where the wiper terminal is to connect. An additional control signal is used to connect an additional wiper to one of the two separate wiper terminals permitting the connection of the two resistor strings in series.

Abstract: A communication module comprises a substantially token-shaped body with first and second electrically conductive surface areas. The first and second surface areas are electrically isolated from each other and circuitry is positioned in the cavity within the substantially token-shaped body, and has connections to said first and second areas. The substantially token-shaped body has a perimeter around it. The first and second electrically conductive surface areas form a substantial portion of the substantially token-shaped body. The first and second electrically conductive surface areas form a cavity. One of the surface areas forming a flange around the perimeter of the substantially token-shaped body. The flange preferably resides in one geometric plane. The circuitry provides for the receipt and transmission of digital signals that are determined as voltage differences between said first and second areas.

Abstract: An integrated circuit temperature detector (thermometer) uses a temperature dependent oscillator to count up to a fixed number and thereby generate a time interval indicative of the temperature (a temperature-to-time converter). The time-to-number converter provides a numeric temperature output. Counting oscillations of a relatively temperature independent oscillator for the time interval may digitize the temperature measurement. Calibration and successive approximation iterations permit simple hardware to achieve good accuracy.

Abstract: An integrated circuit memory which includes at least some RAM/ROM hybrid columns. The RAM/ROM hybrid cells operate as normal SRAM cells forever, unless and until they are programmed to operate as ROM cells. Thus users who need the extra security permitted by ROM encoding can have this capability, while users who do not need ROM encoding can use off-the-shelf parts as RAM only.

Abstract: A system architecture which provides efficient data communication, over a one-wire bus, with a portable data module which does not necessarily include any accurate time delay circuit whatsoever. The time delay circuit in the module can be extremely crude. An open-collector architecture is used, with electrical relations defined to absolutely minimize the drain on the portable module's battery. A protocol has been specified so that the module never sources current to the data line of the one-wire bus, but only sinks current. The protocol includes signals for read; write-zero; write-one; and reset. Each one-bit transaction is initiated by a falling edge of a voltage signal from a host. The time delay circuit in the module defines a delay, after which (in write mode) the module tests the data state of the data line. In read mode, after a falling edge of a voltage signal from the host the module does or does not turn on a pull-down transistor, depending on the value of the bit read.

Abstract: An integrated circuit temperature detector (thermometer) uses a temperature dependent oscillator to count up to a fixed number and thereby generate a time interval indicative of the temperature (a temperature-to-time converter). The time-to-number converter provides a numeric temperature output. Counting oscillations of a relatively temperature independent oscillator for the time interval may digitize the temperature measurement. Calibration and successive approximation iterations permit simple hardware to achieve good accuracy.

Abstract: A memory controller for supplying backup battery power when a main power supply voltage drops together with programmable plus power fail write protection. The controller includes supravoltage induced sleep mode operation, MOS switching between backup batteries during backup operation based on battery voltage levels and discharge circuitry for battery disposal.

Abstract: A digital potentiometer, in which the three terminals of the potentiometer are all free-floating. The position of the wiper is selected by a control signal received on a serial port. A change is made in the effective position of the wiper until the reset-bar signal goes low. Thus, the value of the potentiometer can be directly changed to any desired value, without intermediate incrementing steps. Moreover, this control arrangement allows multiple such potentiometers to share the same serial control bus, in a "daisy chain" configuration. This has the advantage that all of the potentiometers on the serial control bus will change their values at the same time. (This is advantageous, for example, in systems where such potentiometers are used to set the gain characteristics of multiple op amps.

Abstract: A CPU (28) accesses remotely disposed RAM (12) through a common serial data link. The RAM is interfaced to the common data link under the control of an arbiter circuit (10). The arbiter includes a protocol shift register (31) for receiving control information, ID information, and address information for the RAM. The incoming ID information is compared with an ID template (37), and:If a match IS present:Read/Write access to the RAM is allowed, andRead/Write access to the ID template is allowed;If a match is NOT present:NO access to the RAM is allowed,Read-Only access to the ID template is allowed.

Abstract: An integrated circuit containing two digital potentiometers with each potentiometer including a passive resistor string with tap points. Tap point selection is programmed through a three-wire serial port. An output multiplexing the selected tap points permits tying the two potentiometers in series to form a single potentiometer of twice the size.

Abstract: An electronic key integrated circuit which includes three independently addressable partitions of secure memory. Each of these three partitions can function as a separate "subkey." Each of the subkeys is independently password-protected.In addition to the secure subkey memory partitions, the integrated circuit also contains a read/write "scratchpad" memory, which is the same size as each of the subkeys. After data has been written into the scratchpad (and verified if desired), it can be copied, as a block, onto one of the subkey partitions. However, to perform such a block move the password of the target subkey must also be specified.

Abstract: A system architecture which provides efficient data communication, over a one-wire bus, with a portable data module which does not necessarily include any accurate time delay circuit whatsoever. The time delay circuit in the module can be extremely crude. An open-collector architecture is used, with electrical relations defined to absolutely minimize the drain on the portable module's battery. A protocol has been specified so that the module never sources current to a data line of the one-wire bus, but only sinks current. The protocol includes signals for read; write-zero; write-one; and reset. Each one-bit transaction is initiated by a falling edge of a voltage signal from the host. The time delay circuit in the module defines a delay, after which (in write mode) the module tests the data state of the data line. In read mode, after a falling edge of a voltage signal from the host the module does or does not turn on a pull-down transistor, depending on the value of the bit read.

Abstract: An electronic key which includes a pseudo-random number generator. If the correct password is received, the contents of a secure memory will be outputted by the electronic key. However, if an incorrect password is received, that password will be used as a seed value for the pseudo-random number generator, and the resulting value will be outputted.Thus, if a copier exercises the key through all possible passwords, the incorrect passwords, as well as the correct password, will result in the same output data every time it is tried.

Abstract: A low-power low-voltage CMOS six-transistor static random access memory (SRAM), which can operate on a power supply voltage which is less than the sum of the NMOS and PMOS threshold voltages, does not include any analog or metastable sense amplifier stages. The selected cell is allowed to pull one of its bitline pair all the way down to ground. Thus, full logic levels appear on the bitline pair. Only one line of the bitline pair is connected to the following gate stage. Perferably bitline percharge transistors are connected to always pull up any unselected bitline pair.

Abstract: A battery-backed integrated circuit, with a double diode structure connected to signal lines. In the double diode structure, a first junction is three-dimensionally enclosed by a second junction, so that minority carriers generated at the first junction will be collected at the second junction. Thus, when a negative transient voltage appears on the signal line, the first junction can be forward biassed to source the needed current from ground, with minimal minority carrier injection.