Abstract: Examples disclosed herein relate to a three-dimensional object to be displayed on a browser. Examples include to acquire, from a remote system, a three-dimensional object to be displayed in a browser of a computing device. The computing device to display an active region edit interface on the browser. The computing device to acquire an edit request for an active region of the three-dimensional object in the active region edit interface. The computing device to provide, to the remote system, the edit request for the active region of the three-dimensional object. The computing device to acquire, from the remote system, an edited three-dimensional active region corresponding to the edit request for the active region. The computing device to display the edited three-dimensional active region as part of the three-dimensional object on the browser.

Abstract: Examples disclosed herein relate to a three-dimensional object to be displayed on a browser. Examples include to acquire, from a remote system, a three-dimensional object to be displayed in a browser of a computing device. The computing device to display an active region edit interface on the browser. The computing device to acquire an edit request for an active region of the three-dimensional object in the active region edit interface. The computing device to provide, to the remote system, the edit request for the active region of the three-dimensional object. The computing device to acquire, from the remote system, an edited three-dimensional active region corresponding to the edit request for the active region. The computing device to display the edited three-dimensional active region as part of the three-dimensional object on the browser.

Abstract: A method of automatically optimizing a hierarchical netlist of integrated circuit cells comprising at least one upper-level cell containing a multiplicity of subsidiary cells of lower hierachical level includes receiving data defining said netlist and timing constraints for it, and establishing abstract timing models for all the subsidiary cells. Timing constraints are propagated to at least one selected subsidiary cell and this cell is optimized by means of a flat optimizer to produced an optimized version of the selected subsidiary cell. The optimized version of the selected cell is inserted into the netlist. The timing constraints denote arrival times for signals at inputs of a cell and required times for signals at outputs of a cell and each abstract timing model of a cell comprises timing parameters which enable a delay time between a specified input of a cell to a specified output of a cell to be computed.

Abstract: A circuit optimization method in which a set of cost functions are stored for each node that indicate the cost of getting signals to that node and the cost of a gate at that node. By "cost", is meant some figure of merit, such as: the maximal delay for a signal to arrive at a node G; or the area of the elements needed to produce the signal at node G. These cost functions enable the circuit to be optimized without the need for a pattern library and the pattern matching process that is typical of other optimization processes, such as the DAGON Node Tiling Procedure.

Abstract: Vector-specific test circuitry is added to an existing circuit design to enable improved fault test coverage by an existing fault test. Each vector-specific test circuit is designed to produce a single output indicative of whether any faults were detected in a plurality of previously unobservable node states produced in response to an associated test vector.

Abstract: A buffer circuit for fanning out a source signal to a plurality of terminals of specified polarities in accordance with specified time constraints is designed by an automated method in which a circuit template is specified in terms of a tree structure. The terminals are ordered in increasing order of required arrival times of the source signal at each of the terminals. A first terminal in a resulting order is assigned to a highest-level potential terminal site of a same polarity as said first terminal, and buffers on a signal path between said first terminal and the source signal are sized so as to satisfy, if possible, a required arrival time of the source signal at said first terminal. So long as required times of arrival are met, additional terminals are placed in like manner.

Abstract: In a computer aided design system, a netlist specifies the integrated circuit's components and a set of interconnecting nodes. Also provided are a set of timing constraints for propagation of signals from specified input nodes to specified output nodes, and a set of signal delays associated with the circuit's components. The automatic circuit layout synthesis process begins by assigning an initial capacitance value to each node. Next, a routing difficulty value is computed, this value comprises a sum of routing difficulty values associated with each of the nodes in the integrated circuit. Capacitance values for the integrated circuit are then adjusted so as to reduce the computed routing difficulty. Finally, the netlist and adjusted capacitance values are passed to a silicon compiler for automatic placement and routing of a circuit having capacitance values not exceeding the adjusted capacitance values.

Abstract: A method estimates the interconnect capacitance of a first net in an integrated circuit. The first step of the method includes the generation of a value which indicates how tightly connected to one another are components connected to the first net. The second step of the method includes the prediction of interconnect capacitance of the first net based on the value generated in the first step and a number representing how many components are connected to the first net.

Abstract: In a computer aided design system, capacitative constraints are defined for the nodes of an integrated circuit. A netlist specifies the integrated circuit's components and a set of interconnecting nodes. Also provided are a set of timing constraints for propagation of signals from specified input nodes to specified output nodes, and a set of signal delays associated with the circuit's components. The process begins by assigning a time delay value and a corresponding initial maximum capacitance value to each circuit node, consistent with the specified timing constraints. Next, a routing difficulty value for the entire circuit, equal to a sum of routing difficulty values associated with the circuits's nodes is computed. Each routing difficulty value is a predefined function of the maximum capacitance value for a corresponding node and the number of circuit components coupled to that node.

Abstract: An integrated circuit includes parity chains which serve as test logic. Each parity chain has a series of XOR gates, where one input to each succeeding XOR gate in a chain is tied to the output of the preceding XOR gate. The remaining inputs are tied to nodes of the main logic, thus defining test points. An error at any one of the test points is reflected in the output of the parity chain. The outputs of the parity chains are arranged as parallel inputs to a linear feedback shift register which provides a serial signature which can be analyzed to detect integrated circuit defects.

Abstract: A method for simulating a levelized logic circuit including an event-controlled feature for marking components to be reevaluated. An evaluation list is formed which lists signals and corresponding components of the logic circuit which are to be reevaluated. A second list is formed of each component and its corresponding output signals. The external input signals are also listed. Each external input signal is tested for change from a previous evaluation and, if so, the corresponding components in the re-evaluation list are marked for reevaluation. Each component, in levelized order, is then tested to determine whether that component is marked for re-evaluation and, if so, that component is re-evaluated and unmarked, and each signal in the component output signal list which has a non-empty re-evaluation list is tested to determine if the value of the signal has changed since the previous evaluation and, if so, all of the components in that signal's reevaluation list are marked for re-evaluation.

Abstract: A simulator for a levelized logic circuit reduces the number of evaluations required. The simulator associates certain lists of signals, called fences, with each component of a logic circuit. A fence is evaluated to determine whether it is active or inactive. Active fences contain signals which have charged since a previous evaluation. Components for active fences are then evaluated by the simulator. Fences are formed by starting with a seed set of signals. If all of the input signals to a component are in one or more fences, a final fence for a component is formed which is the union of the one or more fences. Only signals which can cause an output change on a component are included in fences.