Abstract: An apparatus is provided for controlling the operating mode of control circuitry, such that the control circuitry may change between two operating modes. In an allocation mode, data that is loaded in response to an instruction is allocated into storage circuitry from an intermediate buffer, and the data is read from the storage circuitry. In a non-allocation mode, the data is not allocated to the storage circuitry, and is read directly from intermediate buffer. The control of the operating mode may be performed by mode control circuitry, and the mode may be changed in dependence on the type of instruction that calls the data, and whether the data may be used again in the near future, or whether it is expected to be used only once.

Abstract: Provided herein are nucleic acid trans-splicing molecules (e.g., pre-mRNA trans-splicing molecules (RTMs); RNA exon editing molecules) capable of correcting mutations in the ABCA4 gene. Such molecules are useful in the treatment of disorders such as ABCA4-associated retinal dystrophies (e.g., Stargardt Disease or cone-rod dystrophy). Also described herein are methods of using the nucleic acid trans-splicing molecules described herein to correct mutations in ABCA4, thereby treating disorders associated with mutations in ABCA4 and use of the nucleic acid trans-splicing molecules described herein for treating disorders associated with mutations in ABCA4 and in the preparation of medicaments for the treatment of disorders associated with mutations in ABCA4.

Abstract: A payment processing method uses a credit push for completing a transaction at a terminal device. The process can include scanning an optical code at terminal device using a mobile device to determine creditor bank information. A debtor bank server receives the creditor bank information and provides a credit push request to a payment rail. The payment rail communicates a credit payment transaction request to a creditor bank sever. The creditor bank server identifies the terminal device and instructs completion of the transaction at the terminal device in an amount corresponding to the credit push request. The transaction is initiated at the terminal device. An authentication procedure for facilitating the transaction by communicating the creditor bank information is performed by the mobile device and not by the terminal device.

Abstract: Methods and systems relating to improved processing architectures with pre-staged instructions are disclosed herein. A disclosed processor includes a memory, at least one functional processing unit, a bus, a set of instruction registers configured to be loaded, using the bus, with a set of pre-staged instructions from the memory, and a logic circuit configured to provide the set of pre-staged instructions from the set of instruction registers to the at least one functional processing unit in response to receiving an instruction from the instruction memory.

Abstract: Methods and systems relating to improved processing architectures with pre-staged instructions are disclosed herein. A disclosed processor includes an instruction memory, at least one functional processing unit, a bus, a set of instruction registers configured to be loaded, using the bus, with a set of pre-staged instructions from the instruction memory, and a logic circuit configured to provide the set of pre-staged instructions from the set of instruction registers to the at least one functional processing unit in response to receiving an instruction from the instruction memory.

Abstract: Methods and systems relating to improved processing architectures with pre-staged instructions are disclosed herein. A disclosed processor includes an instruction memory, at least one functional processing unit, a bus, a set of instruction registers configured to be loaded, using the bus, with a set of pre-staged instructions from the instruction memory, and a logic circuit configured to provide the set of pre-staged instructions from the set of instruction registers to the at least one functional processing unit in response to receiving an instruction from the instruction memory.

Abstract: Methods and systems relating to improved processing architectures with pre-staged instructions are disclosed herein. A disclosed processor includes an instruction memory, at least one functional processing unit, a bus, a set of instruction registers configured to be loaded, using the bus, with a set of pre-staged instructions from the instruction memory, and a logic circuit configured to provide the set of pre-staged instructions from the set of instruction registers to the at least one functional processing unit in response to receiving an instruction from the instruction memory.

Abstract: A request node is provided, that includes request circuitry for issuing outgoing memory access requests to a remote node. Status receiving circuitry receives statuses regarding remote memory access requests at the remote node and control circuitry controls at least one of a rate or an aggression at which the outgoing memory access requests are issued to the remote node in dependence on at least some of the statuses. The control circuitry is inhibited from controlling the rate or the aggression until multiple statuses are received.

Abstract: A request node is provided, that includes request circuitry for issuing outgoing memory access requests to a remote node. Status receiving circuitry receives statuses regarding remote memory access requests at the remote node and control circuitry controls at least one of a rate or an aggression at which the outgoing memory access requests are issued to the remote node in dependence on at least some of the statuses. The control circuitry is inhibited from controlling the rate or the aggression until multiple statuses are received.

Abstract: An apparatus is provided that includes cache circuitry that comprises a plurality of cache lines. The cache circuitry treats one or more of the cache lines as trace lines each having correlated addresses and each being tagged by a trigger address. Prefetch circuitry causes data at the correlated addresses stored in the trace lines to be prefetched.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for using location data to identify and provide services in association with items appearing in captured images. One of the methods includes receiving, from a device, an image and location data representing the device's physical location, determining, based on the location data, that a particular set of one or more locations are within a threshold distance of the device's physical location, accessing, for each of the one or more locations in the particular set, item information that indicates one or more items that are associated with the location, determining, based on the accessed item information, that the image likely shows a particular item that is associated with one or more locations in the particular set, and providing, to the device, instructions for presentation of information about (i) the particular item and (ii) one or more locations in the particular set that are associated with the particular item.

Abstract: An apparatus is described, comprising load issuing circuitry configured to issue load operations to load data from memory, and memory ordering tracking storage circuitry configured to store memory ordering tracking information on issued load operations. The apparatus also includes control circuitry configured to access the memory ordering tracking storage circuitry to determine, using the memory ordering tracking information, whether at least one load operation has been issued in disagreement with a memory ordering requirement, and, if so, to determine whether to re-issue one or more issued load operations or to continue issuing load operations despite disagreement with the memory ordering requirement. Furthermore, the control circuitry is capable of merging the memory ordering tracking information for a plurality of issued load operations into a merged entry in the memory ordering tracking storage circuitry.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for a predictive analytics system that provides a mechanism to change the design or implementations of a product manufactured in a supply chain are disclosed. In one aspect, a method includes the actions of receiving training data that includes private information for a node in a supply chain network and information regarding previous decisions related to product change requests for a product manufactured through the supply chain network; training, using the training data, a predictive model configured to render decisions for requests to change a part used in manufacturing the product; receiving a request to change a given part; applying the predictive model to the request to change the given part; determining a decision approving or denying the request; and transmitting the decision to the requesting node.

Abstract: A data processing apparatus is provided that includes a plurality of storage elements. Receiving circuitry receives a plurality of incoming data beats from cache circuitry and stores the incoming data beats in the storage elements. At least one existing data beat in the storage elements is replaced by an equal number of the incoming data beats belonging to a different cache line of the cache circuitry. The existing data beats stored in said plurality of storage elements form an incomplete cache line.

Abstract: An apparatus is described, comprising load issuing circuitry configured to issue load operations to load data from memory, and memory ordering tracking storage circuitry configured to store memory ordering tracking information on issued load operations. The apparatus also includes control circuitry configured to access the memory ordering tracking storage circuitry to determine, using the memory ordering tracking information, whether at least one load operation has been issued in disagreement with a memory ordering requirement, and, if so, to determine whether to re-issue one or more issued load operations or to continue issuing load operations despite disagreement with the memory ordering requirement. Furthermore, the control circuitry is capable of merging the memory ordering tracking information for a plurality of issued load operations into a merged entry in the memory ordering tracking storage circuitry.

Abstract: Implementations are directed to methods, systems, apparatus, and computer programs for generation of a three-dimensional (3D) animation by receiving a user input defining a two-dimensional (2D) representation of a plurality of elements, processing, by the one or more processors, the 2D representation to classify the plurality of elements in symbolic elements and action elements, generating, by the one or more processors, based on the symbolic elements, the action elements, and a set of rules a 3D animation corresponding to the 2D representation, and transmitting, by the one or more processors, the 3D animation to an extended reality device for display.

Abstract: Storage circuitry is provided, that is designed to form part of a memory hierarchy. The storage circuitry comprises receiver circuitry for receiving a request to obtain data from the memory hierarchy. Transfer circuitry causes the data to be stored at a selected destination in response to the request, wherein the selected destination is selected in dependence on at least one selection condition. Tracker circuitry tracks the request while the request is unresolved. If at least one selection condition is met then the destination is the storage circuitry and otherwise the destination is other storage circuitry in the memory hierarchy.

Abstract: Apparatuses and methods for prefetch generation are disclosed. Prefetching circuitry receives addresses specified by load instructions and can cause retrieval of a data value from an address before that address is received. Stride determination circuitry determines stride values as a difference between a current address and a previously received address. Plural stride values corresponding to a sequence of received addresses are determined. Multiple stride storage circuitry stores the plurality of stride values determined by the stride determination circuitry. New address comparison circuitry determines whether a current address corresponds to a matching stride value based on the plurality of stride values stored in the multiple stride storage circuitry. Prefetch initiation circuitry can causes a data value to be retrieved from a further address, wherein the further address is the current address modified by the matching stride value of the plurality of stride values.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for using location data to identify and provide services in association with items appearing in captured images. One of the methods includes receiving, from a device, an image and location data representing the device's physical location, determining, based on the location data, that a particular set of one or more locations are within a threshold distance of the device's physical location, accessing, for each of the one or more locations in the particular set, item information that indicates one or more items that are associated with the location, determining, based on the accessed item information, that the image likely shows a particular item that is associated with one or more locations in the particular set, and providing, to the device, instructions for presentation of information about (i) the particular item and (ii) one or more locations in the particular set that are associated with the particular item.

Abstract: Implementations are directed to methods, systems, apparatus, and computer programs for generation of a three-dimensional (3D) animation by receiving a user input defining a two-dimensional (2D) representation of a plurality of elements, processing, by the one or more processors, the 2D representation to classify the plurality of elements in symbolic elements and action elements, generating, by the one or more processors, based on the symbolic elements, the action elements, and a set of rules a 3D animation corresponding to the 2D representation, and transmitting, by the one or more processors, the 3D animation to an extended reality device for display.