Patents by Inventor Robert E. Belke, Jr.

Robert E. Belke, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6752015
    Abstract: The present invention involves a device for detecting a condition of a flowing fluid within a vehicle having reduced sulfur ingress. The device includes a base plate having a receiving surface and a circumferential edge and a printed circuit board disposed on the receiving surface of the base plate. The device further includes a housing having peripheral side walls attaching to the receiving surface adjacent the circumferential edge to define a peripheral interface enclosing the printed circuit board within the housing. The device further includes an adhesive material disposed at the interface to adhere the housing to the base plate. The adhesive material has a predetermined thermal expansion coefficient and a predetermined elastic modulus to reduce fluid ingress through the interface and to accommodate thermal expansions of the base plate and the housing.
    Type: Grant
    Filed: September 24, 2002
    Date of Patent: June 22, 2004
    Assignee: Visteon Global Technologies, Inc.
    Inventors: David J. Thompson, Robert E. Belke, Jr., Edward P. McLeskey
  • Patent number: 6449839
    Abstract: A method for forming connections within a multi-layer electronic circuit board 10. In one non-limiting embodiment, the method includes selectively forming air bridges over portions of the circuit board 10 and selectively collapsing the air bridges with a metallurgical bonding tool, effective to interconnect layers of the circuit board 10.
    Type: Grant
    Filed: September 6, 2000
    Date of Patent: September 17, 2002
    Assignee: Visteon Global Tech., Inc.
    Inventors: Andrew Z. Glovatsky, Thomas Krautheim, Robert E. Belke, Jr., Vivek Amir Jairazbhoy, Cuong V. Pham
  • Patent number: 5738797
    Abstract: A three dimensional multi-layer circuit structure is formed by partially etching a foil having a coating. A pre-circuit is formed by providing a metal foil, applying a photodefinable photoresist to each side of the metal foil, selectively exposing and developing the photoresist leaving exposed areas and unexposed areas and, plating the unexposed areas with a second metal. The pre-circuit is placed in an etching solution and removed after the etching solution partially etches the metal foil to undercut the second metal. The partially etched pre-circuit is then bent into a predetermined shape. The partially etched pre-circuit is then inserted into a mold cavity so that at least one surface of the circuit structure is adjacent to the mold. The mold is filled with a polymer resin so that the polymer resin encapsulates at least a portion of the partially etched pre-circuit and substantially fills the undercut.
    Type: Grant
    Filed: May 17, 1996
    Date of Patent: April 14, 1998
    Assignee: Ford Global Technologies, Inc.
    Inventors: Robert E. Belke, Jr., Michael G. Todd, Andrew Z. Glovatsky, Alice D. Zitzmann
  • Patent number: 5579573
    Abstract: Method for fabricating an undercoated chip electrically interconnected to a substrate. The method includes the initial step of depositing a predetermined quantity of a liquid undercoat material onto the chip or the substrate. The method continues with the step of interconnecting the chip to the substrate so as to form an electrical interconnection bond therebetween. Finally, the method concludes with the step of heating, reflowing and curing the undercoat material during or after the step of electrically interconnecting the chip to the substrate.
    Type: Grant
    Filed: October 11, 1994
    Date of Patent: December 3, 1996
    Assignee: Ford Motor Company
    Inventors: Jay D. Baker, Cuong V. Pham, Robert E. Belke, Jr.
  • Patent number: 4806704
    Abstract: The invention relates to a metal matrix composite used to support and/or enclose discrete electronic semiconductor devices, monolithic integrated circuits, hybrid circuits, and multi-layer printed wiring boards. The matrices herein disclosed employ aluminum as the matrix with Beta Eucryptite as the additive in a volume percent of up to 60. The preferred range of from 55 to 45 percent by volume of the additive has a coefficient of thermal expansion matching the common semiconductor materials and common ceramics used for electronic enclosures. The composite uses low cost materials, and due to the affinity of the additive to aluminum is easily prepared. The resulting structures have good thermal conductivity and low weight.
    Type: Grant
    Filed: June 8, 1987
    Date of Patent: February 21, 1989
    Assignee: General Electric Company
    Inventors: Robert E. Belke, Jr., George F. Trojanowski, Louis Zakraysek
  • Patent number: 4679122
    Abstract: A novel metal core printed circuit board and a method of making it are described. The circuit board comprises a metal substrate, a patternable metal foil, and an insulating layer of thermoplastic resin whose glass transition temperature is exceeded during assembly under pressure to bond the resin to the metal substrate and to the foil by high temperature wetting. The circuit board also provides holes whose interior is lined with a resin united fusing to the resin in the insulating layer by high temperature wetting accompanied by pressure. The thermoplastic resin is a polyetherimide engineering plastic. The layers of the printed circuit board described above, including any additional layers of insulating resin and foil, may be bonded in a single step in a laminating press.
    Type: Grant
    Filed: July 11, 1986
    Date of Patent: July 7, 1987
    Assignee: General Electric Company
    Inventors: Robert E. Belke, Jr., Raymond A. Shirk, Hsiu H. Lin, Louis Zakraysek
  • Patent number: 4466874
    Abstract: The invention deals with a method of electroding a poly(vinylidene fluoride) solid in a piezoelectric application. The electroding method entails surface preparation of the poly(vinylidene fluoride) by a variety of steps including plasma etching to create temporary molecular scale surface irregularities followed by sputtering a metallic layer before deterioration of the plasma etched surface. The chromium may be the initial metal sputtered, followed by a sputtered copper layer, followed in turn by at least one heavier electrodeposited conductive layer. The method may be conducted without deterioration of the piezoelectric properties of the material. The method has been found to provide very good adhesion between the electrode and the PVF.sub.2 surface.
    Type: Grant
    Filed: September 29, 1983
    Date of Patent: August 21, 1984
    Assignee: General Electric Company
    Inventors: Robert E. Belke, Jr., Richard J. Hill, Raymond A. Shirk, David P. Smith
  • Patent number: 4465547
    Abstract: The invention deals with a method of bonding a poly(vinylidene fluoride) solid to a variety of solid substrates, in an application typically using the piezoelectric properties of the material. The bonding method entails surface preparation of the poly(vinylidene fluoride) by a variety of steps including activation of the surface by plasma etching to cause the surface to wet the adhesive used in the bonding process. The bonding method produces bonds of increased strength and having good electrical properties.
    Type: Grant
    Filed: September 29, 1983
    Date of Patent: August 14, 1984
    Assignee: General Electric Company
    Inventors: Robert E. Belke, Jr., Raymond A. Shirk