Patents by Inventor Robert E. Busch
Robert E. Busch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7464217Abstract: A design structure for content addressable memory including a first array of memory cells, and a second array of memory cells. A search logic circuit is configured to prevent a discharge of the second array of memory cells when a search of the first array of memory cells finds certain data.Type: GrantFiled: September 6, 2007Date of Patent: December 9, 2008Assignee: International Business Machines CorporationInventors: Geordie M. Braceras, Robert E. Busch
-
Patent number: 7337268Abstract: A content addressable memory including a first array of memory cells, and a second array of memory cells. A search logic circuit is configured to prevent a discharge of the second array of memory cells when a search of the first array of memory cells finds certain data.Type: GrantFiled: September 19, 2006Date of Patent: February 26, 2008Assignee: International Business Machines CorporationInventors: George M Braceras, Robert E Busch
-
Patent number: 7120732Abstract: A structure, apparatus and method for reducing the power requirement of CAM memories, where the memory cells of the memory array are divided into groups of rows of multiple memory segments. Each memory segment has its own search driver and is searched separately. The memory segments are also searched in a prescribed order. If the search data is found in a particular memory segment, the search is stopped, leaving subsequent memory segments unsearched. By searching memory segments only until the search data is found, match lines of the subsequent memory segments are not unnecessarily discharge and recharged thereby reducing the current demands placed upon the power supply by the CAM memory. A selectable option to do a full search of the CAM memory is also provided for when the power supply is able to meet such current demands.Type: GrantFiled: February 24, 2004Date of Patent: October 10, 2006Assignee: International Business Machines CorporationInventors: George M. Braceras, Robert E. Busch
-
Patent number: 7117400Abstract: An integrated circuit including: a set of bitlines; a set of data lines; means for coupling each respective data line to a first respective bitline or to a second respective bitline based on a steering signal, the second respective bitline being adjacent to the first respective bitline; and means for maintaining the first respective bitline at a desired potential after the data line is coupled to the second bitline.Type: GrantFiled: November 13, 2002Date of Patent: October 3, 2006Assignee: International Business Machines CorporationInventors: Kevin A. Batson, Robert E. Busch, Garrett S. Koch, Fred J. Towler, Reid A. Wistort
-
Patent number: 6941435Abstract: An integrated circuit and a method of reconfiguring an integrated circuit in which multiple configuration sets, each including a plurality of register settings, are stored on the chip. Selection of at least a portion of a configuration set allows for quicker and easier retrieval and loading of register settings, and reduces the complexity and size of the higher level system control program. In an alternative embodiment, at least a portion of a configuration set that is stored on the chip can be directly loaded to at least one device to be controlled to eliminate the need for the set of registers.Type: GrantFiled: January 21, 2003Date of Patent: September 6, 2005Assignee: International Business Machines CorporationInventors: Anthony R. Bonaccio, Robert E. Busch, Barton E. Green, Frank R. Keyser, III, Troy A. Seman
-
Patent number: 6791855Abstract: The present invention provides a memory architecture that allows memory checking and replacement of defective words by spare elements already provided on the chip that do not increase the chip size. The method of the invention uses a separate redundant array architecture to provide address translation, so that the redundant entries are represented as the correct entry index that they are replacing.Type: GrantFiled: August 14, 2003Date of Patent: September 14, 2004Assignee: International Business Machines CorporationInventors: Kevin A. Batson, Robert E. Busch, Gary S. Koch, Fred J. Towler, Reid A. Wistort
-
Publication number: 20040153899Abstract: An integrated circuit including: a set of bitlines; a set of data lines; means for coupling each respective data line to a first respective bitline or to a second respective bitline based on a steering signal, the second respective bitline being adjacent to the first respective bitline; and means for maintaining the first respective bitline at a desired potential after the data line is coupled to the second bitline.Type: ApplicationFiled: November 13, 2002Publication date: August 5, 2004Applicant: International Business Machines CorporationInventors: Kevin A. Batson, Robert E. Busch, Garrett S. Koch, Fred J. Towler, Reid A. Wistort
-
Publication number: 20040143715Abstract: An integrated circuit and a method of reconfiguring an integrated circuit in which multiple configuration sets, each including a plurality of register settings, are stored on the chip. Selection of at least a portion of a configuration set allows for quicker and easier retrieval and loading of register settings, and reduces the complexity and size of the higher level system control program. In an alternative embodiment, at least a portion of a configuration set that is stored on the chip can be directly loaded to at least one device to be controlled to eliminate the need for the set of registers.Type: ApplicationFiled: January 21, 2003Publication date: July 22, 2004Applicant: International Business Machines CorporationInventors: Anthony R. Bonaccio, Robert E. Busch, Barton E. Green, Frank R. Keyser, Troy A. Seman
-
Patent number: 6760240Abstract: A method and structure for an array of content addressable memory (CAM) cells is disclosed. Each of the CAM cells has a search line and a bitline parallel to the search line. Across the array, search lines and bit lines of the CAM cells are interdigitated so that the search lines and bitlines alternate across the array. CAM cell macro's are inverted with respect to adjacent macros to balance parasitic capacitances across the array.Type: GrantFiled: November 22, 2002Date of Patent: July 6, 2004Assignee: International Business Machines CorporationInventors: Robert E. Busch, Albert M. Chu, Ezra D. B. Hall, Paul C. Parries, Daryl M. Seizter
-
Patent number: 6760881Abstract: A method for combining a refresh operation with a parity validation for a DRAM-based content addressable memory (CAM) is disclosed. In an exemplary embodiment of the invention, the method includes implementing the memory refresh operation and examining a word included within the CAM. A determination is made as to whether data contained within the word constitutes valid data. If the data contained within the word does not constitute valid data, then the parity validation is bypassed. However, if the data contained within the word does constitute valid data, then the parity validation is implemented. The parity validation further includes reading the data contained within the word, generating a parity bit from the data contained within the word, and comparing the generated parity bit with a previously stored parity bit. If the parity validation is implemented and if the generated parity bit does not match the previously stored parity bit, then the data contained within the word is invalidated.Type: GrantFiled: October 16, 2001Date of Patent: July 6, 2004Assignee: International Business Machines CorporationInventors: Kevin A. Batson, Robert E. Busch, Albert M. Chu, Ezra D. B. Hall
-
Publication number: 20040100830Abstract: A method and structure for an array of content addressable memory (CAM) cells is disclosed. Each of the CAM cells has a search line and a bitline parallel to the search line. Across the array, search lines and bit lines of the CAM cells are interdigitated so that the search lines and bitlines alternate across the array. CAM cell macro's are inverted with respect to adjacent macros to balance parasitic capacitances across the array.Type: ApplicationFiled: November 22, 2002Publication date: May 27, 2004Applicant: International Business Machines CorporationInventors: Robert E. Busch, Albert M. Chu, Ezra D. B. Hall, Paul C. Parries, Daryl M. Seizter
-
Patent number: 6728123Abstract: The present invention provides a memory architecture that allows memory checking and replacement of defective words by spare elements already provided on the chip that do not increase the chip size. The method of the invention uses a separate redundant array architecture to provide address translation, so that the redundant entries are represented as the correct entry index that they are replacing.Type: GrantFiled: April 15, 2002Date of Patent: April 27, 2004Assignee: International Business Machines CorporationInventors: Kevin A. Batson, Robert E. Busch, Gary S. Koch, Fred J. Towler, Reid A. Wistort
-
Publication number: 20040052134Abstract: The present invention provides a memory architecture that allows memory checking and replacement of defective words by spare elements already provided on the chip that do not increase the chip size. The method of the invention uses a separate redundant array architecture to provide address translation, so that the redundant entries are represented as the correct entry index that they are replacing.Type: ApplicationFiled: August 14, 2003Publication date: March 18, 2004Inventors: Kevin A. Batson, Robert E. Busch, Gary S. Koch, Fred J. Towler, Reid A. Wistort
-
Patent number: 6687144Abstract: A high-reliability content & addressable memory using a shadow content-addressable memory (CAM) array in parallel with a primary CAM array to increase the reliability of CAM searches. The reliability of CAM searches has been less than desired because of random environmental influences that corrupt data. The shadow CAM is written, read, and searched in parallel with the primary CAM. The search results from the parallel searches are compared and, if identical, are declared valid. If the search results are not equal, corrective action is initiated. The high-reliability content-addressable memory may be used with or without priority encoders.Type: GrantFiled: May 6, 2003Date of Patent: February 3, 2004Assignee: International Business Machines CorporationInventors: Kevin A. Batson, Geordie M Braceras, Robert E. Busch, Gary S. Koch
-
Patent number: 6650561Abstract: A high-reliability content-addressable memory using a shadow content-addressable memory (CAM) array in parallel with a primary CAM array to increase the reliability of CAM searches. The reliability of CAM searches has been less than desired because of random environmental influences that corrupt data. The shadow CAM is written, read, and searched in parallel with the primary CAM. The search results from the parallel searches are compared and, if identical, are declared valid. If the search results are not equal, corrective action is initiated. The high-reliability content-addressable memory may be used with or without priority encoders.Type: GrantFiled: January 30, 2002Date of Patent: November 18, 2003Assignee: International Business Machines CorporationInventors: Kevin A. Batson, Geordie M. Braceras, Robert E. Busch, Gary S. Koch
-
Publication number: 20030202371Abstract: The present invention uses a shadow content-addressable memory (CAM) array in parallel with a primary CAM array to increase the reliability of CAM searches. The reliability of CAM searches has been less than desired because of random environmental influences that corrupt data. The shadow CAM is written, read, and searched in parallel with the primary CAM. The search results from the parallel searches are compared and, if identical, are declared valid. If the search results are not equal, corrective action is initiated. The invention may be used with or without priority encoders.Type: ApplicationFiled: May 6, 2003Publication date: October 30, 2003Inventors: Kevin A. Batson, Geordie M. Braceras, Robert E. Busch, Gary S. Koch
-
Publication number: 20030193822Abstract: The present invention provides a memory architecture that allows memory checking and replacement of defective words by spare elements already provided on the chip that do not increase the chip size. The method of the invention uses a separate redundant array architecture to provide address translation, so that the redundant entries are represented as the correct entry index that they are replacing.Type: ApplicationFiled: April 15, 2002Publication date: October 16, 2003Applicant: International Business Machines CorporationInventors: Kevin A. Batson, Robert E. Busch, Gary S. Koch, Fred J. Towler, Reid A. Wistort
-
Publication number: 20030142525Abstract: The present invention uses a shadow content-addressable memory (CAM) array in parallel with a primary CAM array to increase the reliability of CAM searches. The reliability of CAM searches has been less than desired because of random environmental influences that corrupt data. The shadow CAM is written, read, and searched in parallel with the primary CAM. The search results from the parallel searches are compared and, if identical, are declared valid. If the search results are not equal, corrective action is initiated. The invention may be used with or without priority encoders.Type: ApplicationFiled: January 30, 2002Publication date: July 31, 2003Applicant: International Business Machines CorporationInventors: Kevin A. Batson, Geordie M. Braceras, Robert E. Busch, Gary S. Koch
-
Publication number: 20030074630Abstract: A method for combining a refresh operation with a parity validation for a DRAM-based content addressable memory (CAM) is disclosed. In an exemplary embodiment of the invention, the method includes implementing the memory refresh operation and examining a word included within the CAM. A determination is made as to whether data contained within the word constitutes valid data. If the data contained within the word does not constitute valid data, then the parity validation is bypassed. However, if the data contained within the word does constitute valid data, then the parity validation is implemented. The parity validation further includes reading the data contained within the word, generating a parity bit from the data contained within the word, and comparing the generated parity bit with a previously stored parity bit. If the parity validation is implemented and if the generated parity bit does not match the previously stored parity bit, then the data contained within the word is invalidated.Type: ApplicationFiled: October 16, 2001Publication date: April 17, 2003Inventors: Kevin A. Batson, Robert E. Busch, Albert M. Chu, Ezra D.B. Hall
-
Patent number: 6501675Abstract: A fast DRAM memory uses ground-sensing as opposed to traditional Vdd/2 sensing. A selected DRAM cell connects to a bit-line true (BLT) or a bit-line complement (BLC). At the start of each cycle the BLT and BLC are restored to ground potential. A pair of alternating reference cells are provided for each bit-line. When a selected DRAM cell is connected either BLT or BLC the first reference cell in the pair is connected to the other bitline to provide a reference voltage to the other bitline which can be compared to the voltage provided by the selected DRAM cell. On a subsequent cycle using the same bitline the second reference cell in the pair is used. Thus it is not necessary to wait for the first reference cell to recharge prior to beginning the next cycle. Switching between the first and second reference cells in the pair alternates in this manner resulting in faster cycle time.Type: GrantFiled: May 14, 2001Date of Patent: December 31, 2002Assignee: International Business Machines CorporationInventors: Harold Pilo, Robert E. Busch