Patents by Inventor Robert E. Frickey
Robert E. Frickey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190279730Abstract: An apparatus is described. The apparatus includes a solid state drive having multiple three dimensional stacked FLASH memory chips and controller circuitry. The controller circuitry is to implement wear leveling of storage cells of the FLASH memory chips at a granularity of segments of blocks of said FLASH memory chips that are coupled to a same word line and source gate source node to diminish word line read disturb errors.Type: ApplicationFiled: March 19, 2019Publication date: September 12, 2019Inventors: Ning WU, Robert E. FRICKEY
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Patent number: 10236069Abstract: An apparatus is described. The apparatus includes a storage device having multiple non volatile memory chips and controller circuitry. The controller circuitry is to implement wear leveling of storage cells of the non volatile memory chips at a granularity of segments of storage cell arrays of the non volatile memory chips that share a same disturber node and that are coupled to a same storage cell array wire to diminish disturb errors.Type: GrantFiled: June 20, 2017Date of Patent: March 19, 2019Assignee: Intel CorporationInventors: Ning Wu, Robert E. Frickey
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Publication number: 20190042112Abstract: Embodiments of the present disclosure may relate to a data storage controller that may include a non-volatile memory, and a processor coupled with the non-volatile memory to perform a scan of a plurality of non-volatile memory dies in a multi-die memory package to detect one or more defective non-volatile memory dies, where an individual non-volatile memory die of the plurality of non-volatile memory dies is defective if the individual non-volatile memory die has a number of bad blocks that exceeds a predefined threshold, and store one or more defective die indicators in a die topology in the non-volatile memory based at least in part on the scan, where the one or more defective die indicators correspond to the one or more defective non-volatile memory dies. Other embodiments may be described and/or claimed.Type: ApplicationFiled: March 20, 2018Publication date: February 7, 2019Inventors: Sarvesh Varakabe Gangadhar, Feng Zhu, Xin Guo, Simon D. Ramage, Ning Wu, Robert E. Frickey, III
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Publication number: 20180366204Abstract: An apparatus is described. The apparatus includes a storage device having multiple non volatile memory chips and controller circuitry. The controller circuitry is to implement wear leveling of storage cells of the non volatile memory chips at a granularity of segments of storage cell arrays of the non volatile memory chips that share a same disturber node and that are coupled to a same storage cell array wire to diminish disturb errors.Type: ApplicationFiled: June 20, 2017Publication date: December 20, 2018Inventors: Ning WU, Robert E. FRICKEY
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Patent number: 10067829Abstract: Embodiments include apparatuses, method, and systems for organizing individual memory dice of a memory device into a plurality of virtual dice and designating one of the virtual dice of the memory device for storage of redundancy information. In one embodiment, a memory controller includes memory allocation logic to organize memory resources of individual memory dice of a memory device into a plurality of virtual dice, including a redundancy virtual die for storing redundancy information and a plurality of data virtual dice for storing data. The memory controller may further include input/output logic to write data to the data virtual dice of the non-volatile memory device, and redundancy information logic to generate redundancy information based on the data and to write the redundancy information to the redundancy virtual die of the non-volatile memory device.Type: GrantFiled: December 13, 2013Date of Patent: September 4, 2018Assignee: INTEL CORPORATIONInventors: Robert E. Frickey, III, Wei Fang, Ning Wu
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Patent number: 10025535Abstract: Provided are a method, apparatus, and a system for measuring latency of a storage device. The storage device measures one or more latencies of one or more input/output (I/O) operations received from a host. The storage device transmits information on the one or more latencies to the host.Type: GrantFiled: March 27, 2015Date of Patent: July 17, 2018Assignee: INTEL CORPORATIONInventors: Robert E. Frickey, III, Ye Zhang
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Patent number: 9817600Abstract: According to one configuration, a memory system includes a configuration manager and multiple memory devices. The configuration manager includes status detection logic, retrieval logic, and configuration management logic. The status detection logic receives notification of a failed attempt by a first memory device to be initialized with custom configuration settings stored in the first memory device. In response to the notification, the retrieval logic retrieves a backup copy of configuration settings information from a second memory device in the memory system. The configuration management logic utilizes the backup copy of the configuration settings information retrieved from the second memory device to initialize the first memory device.Type: GrantFiled: December 13, 2016Date of Patent: November 14, 2017Assignee: Intel CorporationInventors: Ning Wu, Robert E. Frickey, Hanmant P. Belgal, Xin Guo
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Patent number: 9679658Abstract: Provided are an apparatus, memory controller and method for performing a block erase operation with respect to a non-volatile memory. A command is generated to perform a portion of the block erase operation. At least one read or write operation is performed after executing the command. An additional instance of the command is executed in response to determining that the block erase operation did not complete after performing the at least one read or write operation.Type: GrantFiled: June 26, 2015Date of Patent: June 13, 2017Assignee: INTEL CORPORATIONInventors: David J. Pelster, Yogesh B. Wakchaure, Xin Guo, Paul D. Ruby, Justin R. Dayacap, Joseph F. Doller, Robert E. Frickey
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Publication number: 20170139631Abstract: According to one configuration, a memory system includes a configuration manager and multiple memory devices. The configuration manager includes status detection logic, retrieval logic, and configuration management logic. The status detection logic receives notification of a failed attempt by a first memory device to be initialized with custom configuration settings stored in the first memory device. In response to the notification, the retrieval logic retrieves a backup copy of configuration settings information from a second memory device in the memory system. The configuration management logic utilizes the backup copy of the configuration settings information retrieved from the second memory device to initialize the first memory device.Type: ApplicationFiled: December 13, 2016Publication date: May 18, 2017Inventors: Ning Wu, Robert E. Frickey, Hanmant P. Belgal, Xin Guo
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Patent number: 9552159Abstract: According to one configuration, a memory system includes a configuration manager and multiple memory devices. The configuration manager includes status detection logic, retrieval logic, and configuration management logic. The status detection logic receives notification of a failed attempt by a first memory device to be initialized with custom configuration settings stored in the first memory device. In response to the notification, the retrieval logic retrieves a backup copy of configuration settings information from a second memory device in the memory system. The configuration management logic utilizes the backup copy of the configuration settings information retrieved from the second memory device to initialize the first memory device.Type: GrantFiled: October 7, 2015Date of Patent: January 24, 2017Assignee: Intel CorporationInventors: Ning Wu, Robert E. Frickey, Hanmant P. Belgal, Xin Guo
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Patent number: 9543019Abstract: Methods, apparatuses and articles of manufacture may receive a first page of data and correct one or more errors in the first page of data to generate a page of corrected data. A program command may then be sent with a second page of data and the page of corrected data, to program a page of memory to store the second page of data.Type: GrantFiled: December 11, 2012Date of Patent: January 10, 2017Assignee: Intel CorporationInventors: Robert E. Frickey, Yogesh B. Wakchaure, Iwen Chao, Xin Guo, Kristopher H. Gaewsky
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Publication number: 20160379715Abstract: Provided are an apparatus, memory controller and method for performing a block erase operation with respect to a non-volatile memory. A command is generated to perform a portion of the block erase operation. At least one read or write operation is performed after executing the command. An additional instance of the command is executed in response to determining that the block erase operation did not complete after performing the at least one read or write operation.Type: ApplicationFiled: June 26, 2015Publication date: December 29, 2016Inventors: David J. PELSTER, Yogesh B. WAKCHAURE, Xin GUO, Paul D. RUBY, Justin R. DAYACAP, Joseph F. DOLLER, Robert E. FRICKEY
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Patent number: 9524774Abstract: An electronic memory or controller may use a first type of read command, addressed to a first page of memory of an electronic memory that includes information to indicate that a second page of memory of the electronic memory has not been programmed and a second type of read command, addressed to the first page of memory, that includes information to indicate that the second page of memory has been programmed. The first page of memory may include a lower page of a multi-level cell (MLC), and the second page of memory may include an upper page of the same MLC. The second page of memory is enabled during a period of time that the first type of read command is used.Type: GrantFiled: November 30, 2015Date of Patent: December 20, 2016Assignee: Intel CorporationInventors: Robert E. Frickey, Yogesh B. Wakchaure, Iwen Chao, Xin Guo, Kristopher H. Gaewsky
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Publication number: 20160283119Abstract: Provided are a method, apparatus, and a system for measuring latency of a storage device. The storage device measures one or more latencies of one or more input/output (I/O) operations received from a host. The storage device transmits information on the one or more latencies to the host.Type: ApplicationFiled: March 27, 2015Publication date: September 29, 2016Inventors: Robert E. FRICKEY, III, Ye ZHANG
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Publication number: 20160155497Abstract: An electronic memory or controller may use a first type of read command, addressed to a first page of memory of an electronic memory that includes information to indicate that a second page of memory of the electronic memory has not been programmed and a second type of read command, addressed to the first page of memory, that includes information to indicate that the second page of memory has been programmed. The first page of memory may include a lower page of a multi-level cell (MLC), and the second page of memory may include an upper page of the same MLC. The second page of memory is enabled during a period of time that the first type of read command is used.Type: ApplicationFiled: November 30, 2015Publication date: June 2, 2016Applicant: Intel CorporationInventors: Robert E. Frickey, Yogesh B. Wakchaure, Iwen Chao, Xin Guo, Kristopher H. Gaewsky
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Patent number: 9354973Abstract: Data management logic allocates a portion such as a single plane of a respective multi-plane non-volatile memory device to store parity information for corresponding data striped across multiple planes of multiple non-volatile memory devices. According to one configuration, the data management logic as discussed herein generates parity data based on (a data stripe of) non-parity data stored in multiple planes of multiple different memory devices. The data management logic stores the parity data in the storage plane allocated to store the parity information. Additional configurations include: reserving a parity block amongst multiple non-parity data blocks to store parity data and reserving a parity page amongst multiple non-parity data pages to store parity data.Type: GrantFiled: March 13, 2013Date of Patent: May 31, 2016Assignee: Intel CorporationInventors: Yogesh B. Wakchaure, Xin Guo, Robert E. Frickey
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Publication number: 20160054925Abstract: According to one configuration, a memory system includes a configuration manager and multiple memory devices. The configuration manager includes status detection logic, retrieval logic, and configuration management logic. The status detection logic receives notification of a failed attempt by a first memory device to be initialized with custom configuration settings stored in the first memory device. In response to the notification, the retrieval logic retrieves a backup copy of configuration settings information from a second memory device in the memory system. The configuration management logic utilizes the backup copy of the configuration settings information retrieved from the second memory device to initialize the first memory device.Type: ApplicationFiled: October 7, 2015Publication date: February 25, 2016Inventors: Ning Wu, Robert E. Frickey, Hanmant P. Belgal, Xin Guo
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Patent number: 9236136Abstract: An electronic memory or controller may use a first type of read command, addressed to a first page of memory of an electronic memory that includes information to indicate that a second page of memory of the electronic memory has not been programmed and a second type of read command, addressed to the first page of memory, that includes information to indicate that the second page of memory has been programmed. The first page of memory may include a lower page of a multi-level cell (MLC), and the second page of memory may include an upper page of the same MLC. The second page of memory is enabled during a period of time that the first type of read command is used.Type: GrantFiled: December 14, 2012Date of Patent: January 12, 2016Assignee: Intel CorporationInventors: Robert E. Frickey, Yogesh B. Wakchaure, Iwen Chao, Xin Guo, Kristopher H. Gaewsky
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Patent number: 9183091Abstract: According to one configuration, a memory system includes a configuration manager and multiple memory devices. The configuration manager includes status detection logic, retrieval logic, and configuration management logic. The status detection logic receives notification of a failed attempt by a first memory device to be initialized with custom configuration settings stored in the first memory device. In response to the notification, the retrieval logic retrieves a backup copy of configuration settings information from a second memory device in the memory system. The configuration management logic utilizes the backup copy of the configuration settings information retrieved from the second memory device to initialize the first memory device.Type: GrantFiled: September 27, 2012Date of Patent: November 10, 2015Assignee: Intel CorporationInventors: Ning Wu, Robert E. Frickey, Hanmant P. Belgal, Xin Guo
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Publication number: 20150169405Abstract: Embodiments include apparatuses, method, and systems for organizing individual memory dice of a memory device into a plurality of virtual dice and designating one of the virtual dice of the memory device for storage of redundancy information. In one embodiment, a memory controller includes memory allocation logic to organize memory resources of individual memory dice of a memory device into a plurality of virtual dice, including a redundancy virtual die for storing redundancy information and a plurality of data virtual dice for storing data.Type: ApplicationFiled: December 13, 2013Publication date: June 18, 2015Inventors: Robert E. Frickey, III, Wei Fang, Ning Wu