Patents by Inventor Robert E. Frickey, III

Robert E. Frickey, III has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190042112
    Abstract: Embodiments of the present disclosure may relate to a data storage controller that may include a non-volatile memory, and a processor coupled with the non-volatile memory to perform a scan of a plurality of non-volatile memory dies in a multi-die memory package to detect one or more defective non-volatile memory dies, where an individual non-volatile memory die of the plurality of non-volatile memory dies is defective if the individual non-volatile memory die has a number of bad blocks that exceeds a predefined threshold, and store one or more defective die indicators in a die topology in the non-volatile memory based at least in part on the scan, where the one or more defective die indicators correspond to the one or more defective non-volatile memory dies. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: March 20, 2018
    Publication date: February 7, 2019
    Inventors: Sarvesh Varakabe Gangadhar, Feng Zhu, Xin Guo, Simon D. Ramage, Ning Wu, Robert E. Frickey, III
  • Patent number: 10067829
    Abstract: Embodiments include apparatuses, method, and systems for organizing individual memory dice of a memory device into a plurality of virtual dice and designating one of the virtual dice of the memory device for storage of redundancy information. In one embodiment, a memory controller includes memory allocation logic to organize memory resources of individual memory dice of a memory device into a plurality of virtual dice, including a redundancy virtual die for storing redundancy information and a plurality of data virtual dice for storing data. The memory controller may further include input/output logic to write data to the data virtual dice of the non-volatile memory device, and redundancy information logic to generate redundancy information based on the data and to write the redundancy information to the redundancy virtual die of the non-volatile memory device.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: September 4, 2018
    Assignee: INTEL CORPORATION
    Inventors: Robert E. Frickey, III, Wei Fang, Ning Wu
  • Patent number: 10025535
    Abstract: Provided are a method, apparatus, and a system for measuring latency of a storage device. The storage device measures one or more latencies of one or more input/output (I/O) operations received from a host. The storage device transmits information on the one or more latencies to the host.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: July 17, 2018
    Assignee: INTEL CORPORATION
    Inventors: Robert E. Frickey, III, Ye Zhang
  • Publication number: 20160283119
    Abstract: Provided are a method, apparatus, and a system for measuring latency of a storage device. The storage device measures one or more latencies of one or more input/output (I/O) operations received from a host. The storage device transmits information on the one or more latencies to the host.
    Type: Application
    Filed: March 27, 2015
    Publication date: September 29, 2016
    Inventors: Robert E. FRICKEY, III, Ye ZHANG
  • Publication number: 20150169405
    Abstract: Embodiments include apparatuses, method, and systems for organizing individual memory dice of a memory device into a plurality of virtual dice and designating one of the virtual dice of the memory device for storage of redundancy information. In one embodiment, a memory controller includes memory allocation logic to organize memory resources of individual memory dice of a memory device into a plurality of virtual dice, including a redundancy virtual die for storing redundancy information and a plurality of data virtual dice for storing data.
    Type: Application
    Filed: December 13, 2013
    Publication date: June 18, 2015
    Inventors: Robert E. Frickey, III, Wei Fang, Ning Wu
  • Patent number: 8332578
    Abstract: A method and system to improve the performance of a multi-level cell (MLC) NAND flash memory. In one embodiment of the invention, the metadata associated with the data stored in a MLC NAND flash memory is stored only in one or more lower pages of the MLC NAND flash memory. The MLC NAND flash memory has lower and upper pages, where the lower pages have a faster programming time or rate than the upper pages in one embodiment of the invention. By storing the metadata only in the pages of the MLC NAND flash memory that have low latencies of programming, the quality of service (QoS) of the MLC NAND flash memory can be improved.
    Type: Grant
    Filed: July 31, 2009
    Date of Patent: December 11, 2012
    Assignee: Intel Corporation
    Inventors: Robert E. Frickey, III, Jonathan M. Hughes
  • Publication number: 20110029718
    Abstract: A method and system to improve the performance of a multi-level cell (MLC) NAND flash memory. In one embodiment of the invention, the metadata associated with the data stored in a MLC NAND flash memory is stored only in one or more lower pages of the MLC NAND flash memory. The MLC NAND flash memory has lower and upper pages, where the lower pages have a faster programming time or rate than the upper pages in one embodiment of the invention. By storing the metadata only in the pages of the MLC NAND flash memory that have low latencies of programming, the quality of service (QoS) of the MLC NAND flash memory can be improved.
    Type: Application
    Filed: July 31, 2009
    Publication date: February 3, 2011
    Inventors: Robert E. Frickey, III, Jonathan M. Hughes