Abstract: A method and frequency converter for a radio rapid frequency signal scanning and including a local oscillator signal synthesis source (112) producing a local oscillator signal (502) with local oscillator bursts (210). The local oscillator bursts (210) contain pulse width modulated RF frequency pulses (602). Each local oscillator burst having, for a pre-determined duration, RF frequency pulses within an effective amplitude above a pre-determined threshold (260). Each local oscillator burst (210) having also has effective amplitude pulse shaping envelope (504) that reduces at least one frequency domain component magnitude (310) of the local oscillator signal (300). A radio frequency mixer (110) receives an RF signal input (104) and the local oscillator signal to produce an output signal (160) at a frequency related to a combination of a frequency of the RF signal input and a frequency of the local oscillator signal.

Abstract: A DPC (300) includes: a frequency source (310) for generating a clock signal; a delay line (320) for receiving the clock signal and generating phase-shifted clock signals at output taps; a digital control device (330) for generating a control signal; and a windowing and selection circuit for generating the output signal, that includes sequential logic devices (500, 510, 520) and a combining network. A method for use in a DPC includes: receiving (400) a control signal based on a desired output signal that identifies a first output tap on the delay line; based on the control signal, selecting (410) at least two output taps on the delay line for receiving at least two different phase-shifted clock signals; and generating (420) an output signal based on the control signal and the received phase-shifted clock signals that is substantially the desired output signal.

Abstract: Improvement of quantization errors that arise in a delay line with finite resolution. A direct digital synthesizer (DDS), which contains a numerically controlled oscillator (NCO) and a digital-to-phase converter (DPC), is placed in the feedback loop of a phase locked loop (PLL). The DDS is used as a fractional divider of the voltage controlled oscillator (VCO) frequency, such that the reference frequency of the DDS is made variable. Alignment of the edges provided by the DDS delay line may then be adjusted. Mismatch errors in the DDS delay line are reduced by utilizing independently tunable delay elements.

Abstract: A frequency generator (100) takes a signal source (clock or carrier) (101) and generates a edge encoded direct digital modulated differential output signal (110). The differential signal (110) is applied to a frequency extension quadrature generator (FEQG) (112). The FEQG (112) includes a fractional differential wavelength delay locked loop (DLL) (280) and a frequency multiplier (240). The DLL (280) generates a control voltage (214) with which to control delays of the edge encoded modulation signal (110). A frequency extended quadrature function is applied to the periodic steady state input signal with edge encoded modulation (110), to provide the output signal set 113.

Abstract: A method and system for managing Digital to Time Conversion (DTC) is provided. The method comprises receiving a first Radio Frequency (RF) signal and a second RF signal. The second RF signal is a phase-shifted first RF signal. The method further comprises converting the first RF signal to a first Intermediate Frequency (IF) signal and the second RF signal to a second IF signal. Further, a time delay between the first IF signal and the second IF signal is estimated based on a time difference measurement technique. The second RF signal is processed based on the estimated time delay to compensate for a delay error associated with the second RF signal.

Abstract: An apparatus and method for eliminating unwanted signal power dissipation in balanced amplifier circuits and for prohibiting unwanted signal power from appearing at the balanced amplifier load is presented. Load impedances to the amplifier power output transistors are maintained very low at unwanted frequencies, and are at an operational impedance level at the fundamental frequency. An impedance network control concept is presented, which may be either manually or automatically implemented.

Abstract: Improvement of quantization errors that arise in a delay line with finite resolution. A direct digital synthesizer (DDS), which contains a numerically controlled oscillator (NCO) and a digital-to-phase converter (DPC), is placed in the feedback loop of a phase locked loop (PLL). The DDS is used as a fractional divider of the voltage controlled oscillator (VCO) frequency, such that the reference frequency of the DDS is made variable. Alignment of the edges provided by the DDS delay line may then be adjusted. Mismatch errors in the DDS delay line are reduced by utilizing independently tunable delay elements.

Abstract: A direct digital synthesizer (DDS) (300) that uses a system for reducing spurious emissions in a digital-to-time converter (DTC) (317). The DDS (300) includes one or more dither sources (307) and a random access memory (RAM) (305). The RAM (305) utilizes a look-up table for storing delay error values by using an output of the look-up table which is combined with the dither source (307) to compensate unequal unit delay values in the DTC (317).

Abstract: Phase shift key modulators (100, 500, 1000, 1400, 1700) are provided in which a multiphase signal source (108, 1402, 1406-1412,1702) is used to generate a plurality of phases of a carrier signal. A selector (110) is used to select one phase or a sequence of phases of the carrier signal to represent each bit pattern that is received from a binary data source (102, 1422). The multiphase signal source preferably comprises a multiphase oscillator that includes a phase locked ring of variable propagation delay inverters (202). Preferably, a phase sequencer (502) is used to select a monotonic sequence of phases to represent each bit pattern. Preferably two phase selectors (110, 1004) are used to simultaneously select two phases of carrier signal, and a phase interpolator (1106) is used to generate a sequence of phases from the two phases selected by the two phase selectors (110, 1004).

Abstract: A signal generator consistent with certain embodiments of the invention has a reference clock (34) producing a periodic sequence of reference clock output pulses. A window generator (38) generates a plurality of time windows through which a selected plurality of the reference clock output pulses are selectively passed as windowed pulses so that the windowed pulses form a selected pattern of pulses. A programmable delay (46) has resolution of delay that has finer time granularity in delay than the period of the clock output pulses. The programmable delay (46) delays each of the windowed pulses by a programmed delay time to thereby provide a timing correction to the windowed pulses to produce an output pattern of pulses.

Abstract: A system and method for clock data recovery for programming direct digital synthesizers is disclosed. A counter is used to calculate a coarse measurement of the clock frequency of a received digital signal, and a tap delay line is used to calculate a fine measurement of the clock frequency of the received digital signal. The coarse and fine measurements are used to calculate a value for programming a direct digital synthesizer to produce a clock signal that is an approximate replica of the clock frequency of the received digital signal.

Abstract: An apparatus and method for eliminating unwanted signal power dissipation in balanced amplifier circuits and for prohibiting unwanted signal power from appearing at the balanced amplifier load is presented. Load impedances to the amplifier power output transistors are maintained very low at unwanted frequencies, and are at an operational impedance level at the fundamental frequency. An impedance network control concept is presented, which may be either manually or automatically implemented.

Abstract: A method is provided for configuring a subscriber unit for operation in a wireless communications system. Information on available wireless services is advertised through well known, and publicly accessible, broadcast media, for the benefit of potential subscribers. A potential subscriber uses a subscriber unit to access the broadcast media and obtain a set of available wireless services (310). The subscriber unit supplies a particular criteria related to one or more of the available wireless services to a brokering agent, and receives from the brokering agent a list of service providers meeting the criteria (320, 330, 340). The subscriber unit then establishes a subscription relationship with a selected service provider, and self-configures to operate in a mode that supports interaction with the service provider (350).

Abstract: Improvement of quantization errors that arise in a delay line with finite resolution. A direct digital synthesizer (DDS), which contains a numerically controlled oscillator (NCO) and a digital-to-phase converter (DPC), is placed in the feedback loop of a phase locked loop (PLL). The DDS is used as a fractional divider of the voltage controlled oscillator (VCO) frequency, such that the reference frequency of the DDS is made variable. Alignment of the edges provided by the DDS delay line may then be adjusted. Mismatch errors in the DDS delay line are reduced by utilizing independently tunable delay elements.

Abstract: A signal generator consistent with certain embodiments of the invention has a reference clock (34) producing a periodic sequence of reference clock output pulses. A window generator (38) generates a plurality of time windows through which a selected plurality of the reference clock output pulses are selectively passed as windowed pulses so that the windowed pulses form a selected pattern of pulses. A programmable delay (46) has resolution of delay that has finer time granularity in delay than the period of the clock output pulses. The programmable delay (46) delays each of the windowed pulses by a programmed delay time to thereby provide a timing correction to the windowed pulses to produce an output pattern of pulses.

Abstract: A frequency extension circuit, consistent with certain embodiments of the present invention has a first delay line (108) having a plurality of taps. The delay line receives a reference clock at an input with a clock rate of FREF. A second delay line (104, 150) also receives the reference clock at an input. A logic circuit (130, 134, . . . , 138, 140) combines signals from the delay line taps of the first delay line (108) with signals from the delay line taps of the second and/or first delay line (104, 150, 108) to produce a collection of clock pulses having a combined clock rate of FREF*2N. At least one of the delay lines can be locked to the reference clock using a delay locked loop. The clock pulses can be logically combined with a seed register (204) contents to produce a recursive sequence or with data for convolutional encoding, or with pilot data for correlation in a CDMA transceiver.

Abstract: A dynamically matched mixer system (200) for use in a direct conversion radio frequency (RF) receiver includes a frequency generator (201, 203, 205) that includes plurality of dividers (407) for providing differential local oscillator reference sources (FLO+ and FLO?) and mitigation frequency reference sources (F1 and F2) from reference oscillator (205). A mixer (209) mixes the differential local oscillator reference sources (FLO+ and FLO?) and the mitigation frequency reference sources (F1 and F2) while dynamic matching units (211, 213) are used for receiving the mitigation frequency reference sources and matching switching parameters of differential input signals (IRF+ and IRF?) and differential baseband output signals (IBB+ and IBB?). The frequencies of the mitigation frequency reference sources (F1 and F2) are selected so as to establish a non-integer relationship to the reference oscillator (201) for mitigating the occurrence of interference with FLO+ and FLO?.

Abstract: A system and a method for providing an input to a distributed power amplifying system are provided. In an embodiment, a distributed power amplifying system includes a plurality of amplifying sections (102, 104, 106, and 108) and a plurality of drivers (110, 112, 114, and 116). Each of the plurality of drivers receives a common transmit signal (118) and an individual control signal (120, 122, 124, and 126). Each of the plurality of drivers independently preconditions the common transmit signal, to provide a transmit output signal (128, 130, 132, and 134) to each of the plurality of amplifying sections. The common transmit signal provided to each of the plurality of drivers is preconditioned, based on the individual control signal.

Abstract: A delay locked loop circuit (200) in which multiple outputs are produced. A single delay line (24) is shared among multiple tap selection circuits (256A, 265B, 265C). Fixed phase shifts (412) can be introduced between multiple outputs. A modulating signal can be used in the tap selection processing to produce digital amplitude, frequency and/or phase modulation.

Abstract: A delay locked loop frequency synthesizer in several embodiments uses a primary delay line element (24) and one or more secondary delay elements (162 . . . 164, 270, 310). In one embodiment, a main delay line (24) is used to coarsely select a frequency output while a secondary delay element (162 . . . 164, 270, 310), either passive or active, is used to increase the resolution of the primary delay line (24). In the passive embodiment, a coarse and fine frequency selection is possible by selecting components from the output taps of the main delay line (24) as a driving signal for the passive secondary delay element (310) to provide the coarse adjustment and selecting an output from the secondary delay element (310) to provide the fine selection.