Patents by Inventor Robert E. Terrill

Robert E. Terrill has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6372623
    Abstract: A process for the fabrication of an integrated circuit assembly, using thin film platinum metallization to provide edge-side contacts suitable for solder ball connections. Three-dimensional laser ablation may be used for patterning metal films. A multi-chip assembly may be formed using orthogonal edge-side mounting on a substrate.
    Type: Grant
    Filed: August 18, 1997
    Date of Patent: April 16, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Emily Ellen Hoffman, Robert E. Terrill, Wesley Michael Wolverton
  • Patent number: 6338973
    Abstract: A mass production process for semiconductor circuits and modules using a combination of thin film platinum metallization dielectric masking, and three-dimensional laser ablation, in conjunction with a solder combinations and melting temperatures. These combinations have been employed for the fabrication of silicon chips as well as connective substrates. Furthermore, spacing films with adhesive properties on both surfaces have been successfully used for assembling multi-chip cubes.
    Type: Grant
    Filed: August 18, 1997
    Date of Patent: January 15, 2002
    Assignee: Texas Instruments Incorporated
    Inventor: Robert E. Terrill
  • Patent number: 6303977
    Abstract: A structure and method for forming a hermetically sealed semiconductor chip having an active and a passive surface and four edge sides, each edge side having only a single plane; said active surface having an integrated circuit including multiple deposited layers and a plurality of contact pads, said contact pads having bondable and non-corrodible surface; said deposited layers having exposed portions at said side edges; a protective overcoat impermeable to moisture overlying said integrated circuit; and a continuous sealant layer impermeable to moisture overlying all area of said four side edges, whereby said edge sides are sealed and said chip is rendered hermetic.
    Type: Grant
    Filed: December 2, 1999
    Date of Patent: October 16, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Walter H. Schroen, Judith S. Archer, Robert E. Terrill
  • Patent number: 6069026
    Abstract: This invention relates to the fabrication and assembly of semiconductor chips, substrates, and modules, and more particularly to methods and apparatus for achieving flexible, low-cost manufacturing. Commercial and military systems today are placing increasing demands on flexible application and reliable operation, as well as on simplified manufacturing.
    Type: Grant
    Filed: August 18, 1997
    Date of Patent: May 30, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: Robert E. Terrill, Judith Sultenfuss Archer
  • Patent number: 5989989
    Abstract: A method of creating a rerouting pattern on a semiconductor die or cube by providing a semiconductor die having an active surface with bond pads thereon and sides. A layer of electrically insulating material is sputtered over the active surface and the sides while exposing the bond pads. Electrically conductive material is formed over the electrically insulating material on the active surface and the sides. A selected portion of the electrically conductive material is removed with an excimer laser. The step of sputtering a layer of electrically insulating material over the active surface and said sides can include the steps of sputtering a layer of electrically insulating material over the active surface including the bond pads and the sides, masking the electrically insulating material to expose the region of the electrically insulating material over the bond pads and ablating the electrically insulating material with an excimer laser at the exposed region down to said bond pads.
    Type: Grant
    Filed: May 30, 1997
    Date of Patent: November 23, 1999
    Assignee: Texas Instruments Incorporated
    Inventor: Robert E. Terrill
  • Patent number: 5673478
    Abstract: A method and an apparatus for I/O reroute include the use of reroute traces (16) and overhangs (20). The reroute traces (16) and overhangs (20) are formed using thick film deposition on dies that have been cut from a wafer.
    Type: Grant
    Filed: November 16, 1995
    Date of Patent: October 7, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Gary L. Beene, Robert E. Terrill
  • Patent number: 4838289
    Abstract: Apparatus and method for cleaning material at the outer edge of an object by applying a solvent for the material to a flat surface adjacent the edge and moving the solvent onto the edge by centrifugal force.
    Type: Grant
    Filed: April 25, 1988
    Date of Patent: June 13, 1989
    Assignee: Texas Instruments Incorporated
    Inventors: Rickie A. Kottman, Robert E. Terrill, Ann E. Wise
  • Patent number: 4685975
    Abstract: Method for cleaning material from the outer edge of an object by applying a solvent for the material to a flat surface adjacent the edge and moving the solvent onto the edge by centrifugal force.
    Type: Grant
    Filed: February 27, 1986
    Date of Patent: August 11, 1987
    Assignee: Texas Instruments Incorporated
    Inventors: Rickie A. Kottman, Robert E. Terrill, Ann E. Wise