Abstract: The disclosed technology can advantageously provide an efficient data recovery system including a plurality of storage nodes including a first storage node and a second storage node, and a storage logic that is coupled to the storage nodes and that manages storage of data on the storage nodes. The storage logic is executable to: receive a data set including data elements including a first set of data elements associated with the first storage node and a second set of data elements associated with the second storage node; generate a first parity of the data set, the first parity including a horizontal parity including a set of horizontal parity entries; and combine the data elements from the data set to produce a skipper parity including a set of skipper parity entries. Combining the data elements includes transforming a subset of the data elements from the data set using an invertible operation, the set of horizontal parity entries being different from the set of skipper parity entries.

Abstract: The present disclosure generally relates to a method of burning a file in a memory device after the file has been read. Once a file has been read, an algorithm uses the memory device to create errors that the error correction code (ECC) cannot decode the error. In creating the error, the entire word line is destroyed physically rather than logically so that retrieving information from that particular word line is no longer possible. In creating the error, adjacent word lines are not affected. The error renders the file burned.

Abstract: In this disclosure, data mapping based on three dimensional lattices that have an improved sum rate (i.e., lifetime capacity) with low read latency is disclosed. During the write, a memory location is written to multiple times prior to erasure. Specifically, for the first write, there are 4/3 bits per cell available for writing, which is about 10.67 kB per cell are used for data storage. Then, for the second write, there is one bit per cell, which is 8 kB per cell for data storage. If considering a block with 128 different cells and writing 32 kB of data, the first write results in 42.66 data writes while the second write results in 32 writes for a total of 74.66 writes. Previously, the number of writes for 32 kB would be 64 writes. Thus, by writing twice prior to erasure, more data can be stored.

Abstract: Technology is provided for updating a data set at a data storage system. In an example storage system, the system stores a data set in a plurality of data storage devices. The system stores parity data at a plurality of parity devices. The system receives update data from a client system for a first section of the data set. The system generates updated parity data based on an original version of the first section of the data set and the update data. The system transmits update parity data to the plurality of parity devices. The system receives update notifications from a plurality of parity devices. The system determines that update notifications have been received from at least a threshold number of parity devices in the plurality of parity devices. In response, the system updates the first section of the data set at the leader data storage device.

Abstract: Various aspects directed towards facilitating error management within a shared non-volatile memory (NVM) architecture are disclosed. Data is stored in an NVM array, and error correction vector (ECV) information associated with the NVM array is stored in a content addressable memory (CAM). A parallel query of the NVM array and the CAM is then performed, which includes a query of the NVM array that yields a readout of the NVM array, and a query of the CAM that yields an ECV corresponding to the readout of the NVM array.

Abstract: Technology is provided for updating a data set at a data storage system. In an example storage system, the system stores a data set in a plurality of data storage devices. The system stores parity data at a plurality of parity devices. The system receives update data from a client system for a first section of the data set. The system generates updated parity data based on an original version of the first section of the data set and the update data. The system transmits update parity data to the plurality of parity devices. The system receives update notifications from a plurality of parity devices. The system determines that update notifications have been received from at least a threshold number of parity devices in the plurality of parity devices. In response, the system updates the first section of the data set at the leader data storage device.

Abstract: The disclosed technology can advantageously provide an efficient data recovery system including a plurality of storage nodes including a first storage node and a second storage node, and a storage logic that is coupled to the storage nodes and that manages storage of data on the storage nodes. The storage logic is executable to: receive a data set including data elements including a first set of data elements associated with the first storage node and a second set of data elements associated with the second storage node; generate a first parity of the data set, the first parity including a horizontal parity including a set of horizontal parity entries; and combine the data elements from the data set to produce a skipper parity including a set of skipper parity entries. Combining the data elements includes transforming a subset of the data elements from the data set using an invertible operation, the set of horizontal parity entries being different from the set of skipper parity entries.

Abstract: A system that implements a near-optimal, reduced-dependency erasure code construction to redundantly distribute computer data across multiple storage nodes includes a memory that stores machine instructions and a processor that executes the machine instructions to group storage segments into discrete groups, each of which corresponds to an individual storage node. The processor further executes the machine instructions to represent regeneration constraints and associate the constraints with storage segments in multiple storage nodes. The processor also executes the machine instructions to generate a parity check matrix based on the regeneration constraints, the associations and the storage segments. The processor additionally executes the machine instructions to construct a generator matrix based on the parity check matrix.

Abstract: Embodiments of the present disclosure generally relate to an improved method and system for error correction in non-volatile memory cells. The method includes writing data to a first location in non-volatile memory from a block of user data stored in DRAM and verifying the written data matches the block of user data. If the written data fails verification, the method further includes writing an error location pointer indicative of one or more error locations in the first location to a second location in non-volatile memory. Writing the one or more error locations to the error location pointer includes verifying the written error location pointer matches an address of the one or more error locations in the first location to ensure integrity of the error location pointer. Use of the error location pointer results in non-volatile memory with increased data rate, decreased read latency and a low probability of data loss.

Abstract: In this disclosure, data mapping based on three dimensional lattices that have an improved sum rate (i.e., lifetime capacity) with low read latency is disclosed. During the write, a memory location is written to multiple times prior to erasure. Specifically, for the first write, there are 4/3 bits per cell available for writing, which is about 10.67 kB per cell are used for data storage. Then, for the second write, there is one bit per cell, which is 8 kB per cell for data storage. If considering a block with 128 different cells and writing 32 kB of data, the first write results in 42.66 data writes while the second write results in 32 writes for a total of 74.66 writes. Previously, the number of writes for 32 kB would be 64 writes. Thus, by writing twice prior to erasure, more data can be stored.

Abstract: The present disclosure generally relates to a method of burning a file in a memory device after the file has been read. Once a file has been read, an algorithm uses the memory device to create errors that the error correction code (ECC) cannot decode the error. In creating the error, the entire word line is destroyed physically rather than logically so that retrieving information from that particular word line is no longer possible. In creating the error, adjacent word lines are not affected. The error renders the file burned.

Abstract: Various aspects directed towards facilitating error management within a shared non-volatile memory (NVM) architecture are disclosed. Data is stored in an NVM array, and error correction vector (ECV) information associated with the NVM array is stored in a content addressable memory (CAM). A parallel query of the NVM array and the CAM is then performed, which includes a query of the NVM array that yields a readout of the NVM array, and a query of the CAM that yields an ECV corresponding to the readout of the NVM array.

Abstract: Embodiments disclosed herein generally relate to an error correction method for non-volatile memory. The error correction method writes data to a first location from a block of user data stored in DRAM. The data written to the first location is verified and errors are identified. Upon determining the number of identified errors exceed a threshold, the block of user data is re-writing to a second location. The data written to the second location is verified and errors are identified. The data written to the first location and the data written to the second location are compared and all discrepancy bits are erased in the comparison. A joint parity check matrix is built with the data written to the first location and the data written to the second location. A code word matrix is built with the comparison. A resultant of the joint parity check matrix and the code word matrix is determined if it is invertible.

Abstract: A method and apparatus are provided for implementing enhanced performance with read before write to phase-change-memory. Each write to PCM is preceded by a read and a calculation to discover a location of any bad bits. The write data is converted to a format that can be corrected for a given number of previously undiscovered bit errors, and the writes are unverified.

Abstract: A system that implements a near-optimal, reduced-dependency erasure code construction to redundantly distribute computer data across multiple storage nodes includes a memory that stores machine instructions and a processor that executes the machine instructions to group storage segments into discrete groups, each of which corresponds to an individual storage node. The processor further executes the machine instructions to represent regeneration constraints and associate the constraints with storage segments in multiple storage nodes. The processor also executes the machine instructions to generate a parity check matrix based on the regeneration constraints, the associations and the storage segments. The processor additionally executes the machine instructions to construct a generator matrix based on the parity check matrix.

Abstract: Embodiments of the present disclosure generally relate to an improved method and system for error correction in non-volatile memory cells. The method includes writing data to a first location in non-volatile memory from a block of user data stored in DRAM and verifying the written data matches the block of user data. If the written data fails verification, the method further includes writing an error location pointer indicative of one or more error locations in the first location to a second location in non-volatile memory. Writing the one or more error locations to the error location pointer includes verifying the written error location pointer matches an address of the one or more error locations in the first location to ensure integrity of the error location pointer. Use of the error location pointer results in non-volatile memory with increased data rate, decreased read latency and a low probability of data loss.

Abstract: Embodiments disclosed herein generally relate to an error correction method for non-volatile memory. The error correction method writes data to a first location from a block of user data stored in DRAM. The data written to the first location is verified and errors are identified. Upon determining the number of identified errors exceed a threshold, the block of user data is re-writing to a second location. The data written to the second location is verified and errors are identified. The data written to the first location and the data written to the second location are compared and all discrepancy bits are erased in the comparison. A joint parity check matrix is built with the data written to the first location and the data written to the second location. A code word matrix is built with the comparison. A resultant of the joint parity check matrix and the code word matrix is determined if it is invertible.

Abstract: A method, apparatus, and storage device are provided for implementing enhanced performance with read before write to phase-change-memory (PCM). Each write to PCM is preceded by a read to avoid write cancellations with urgent reads from nearby locations. For every write, a large block of data is read from PCM, such as an entire partition, prior to the write in PCM. The cache copy of the large block of data is kept in a controller for the duration of write. A read request from the pre-fetched region is provided from the cached copy thereby preventing read interrupt during write operation.

Abstract: A method, apparatus, and storage device are provided for implementing enhanced performance with enhanced phase-change-memory (PCM) read latency through coding. A coding algorithm is used to write data to the PCM including a redundancy chip enabling recovery of inaccessible partition data by reading other partitions. A read operation is served by reading parity lines and computing data for the read operation from a blocked written-to partition.

Abstract: A data storage system includes a memory circuit that has memory cells and a control circuit that is operable to receive data bits provided for storage in the memory cells. The control circuit is operable to receive a first matrix. Each row of the first matrix corresponds to a unique one of the data bits. The control circuit is operable to generate a second matrix having only the rows of the first matrix that correspond to the data bits provided for storage in a subset of the memory cells having stuck-at faults. The control circuit is operable to generate a third matrix having linearly independent columns of the second matrix. The control circuit is operable to encode the data bits to generate encoded data bits and redundant bits using the third matrix.