Patents by Inventor Robert Fehler
Robert Fehler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11935874Abstract: A circuitry is provided. The circuitry may include a power stage including a first transistor and a second transistor, an encapsulation including encapsulation material encapsulating the power stage, wherein the first transistor and the second transistor are arranged in an L-shape with respect to each other along their long axes, and a passive electronic component arranged on or embedded within the encapsulation at least partially, in top view, within a rectangular area defined by the L-shape configuration and further next to the first transistor and next to the second transistor.Type: GrantFiled: July 23, 2021Date of Patent: March 19, 2024Assignee: Infineon Technologies AGInventors: Robert Fehler, Sergey Yuferev
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Publication number: 20240079310Abstract: A method includes providing an interposer that includes an electrically insulating substrate, upper contact pads disposed on an upper surface, and lower contact pads disposed on a lower surface, providing a semiconductor package that includes a semiconductor die embedded within a package body and a plurality of package terminals exposed from the package body, providing a first passive electrical element that comprises first and second terminals, forming a first electrical connection between the first terminal of the first passive electrical element and a first one of the lower contact pads via the interposer, forming a second electrical connection between the second terminal of the first passive electrical element and a first one of the package terminals, and forming a third electrical connection between a second one of the package terminals and a second one of the lower contact pads via the interposer.Type: ApplicationFiled: November 14, 2023Publication date: March 7, 2024Inventors: Angela Kessler, Robert Carroll, Robert Fehler
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Patent number: 11848262Abstract: A semiconductor assembly includes an interposer that includes an insulating substrate, a plurality of upper contact pads on an upper surface of the substrate, and a plurality of lower contact pads on a lower surface of the substrate, a semiconductor package that includes a semiconductor die embedded within a package body and a plurality of package terminals exposed from the package body, a first passive electrical element that includes first and second terminals, a first electrical connection between the first terminal of the first passive electrical element and a first one of the lower contact pads via the interposer, a second electrical connection between the second terminal of the first passive electrical element and a first one of the package terminals, and a third electrical connection between a second one of the package terminals and a second one of the lower contact pads via the interposer.Type: GrantFiled: February 16, 2021Date of Patent: December 19, 2023Assignee: Infineon Technologies AGInventors: Angela Kessler, Robert Carroll, Robert Fehler
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Publication number: 20230253304Abstract: A semiconductor module is provided that includes a low side switch, a high side switch and a control chip. The low side switch and the high side switch are arranged laterally adjacent one another and coupled by a switch node connector to form a half bridge circuit. The switch node connector includes two or more branches that have an arrangement with respect to the low side switch and to the high side switch and that each have a cross-sectional area.Type: ApplicationFiled: April 18, 2023Publication date: August 10, 2023Inventors: Sergey Yuferev, Robert Fehler, Angela Kessler, Gerhard Noebauer, Petteri Palm
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Patent number: 11664304Abstract: A semiconductor module is provided that includes a low side switch, a high side switch and a control chip. The low side switch and the high side switch are arranged laterally adjacent one another and coupled by a switch node connector to form a half bridge circuit. The switch node connector includes two or more branches that have an arrangement with respect to the low side switch and to the high side switch and that each have a cross-sectional area. The arrangement and the cross-sectional area of the two or more branches are selected so as to homogenise the current density distribution within the switch node connector.Type: GrantFiled: October 5, 2021Date of Patent: May 30, 2023Assignee: Infineon Technologies Austria AGInventors: Sergey Yuferev, Robert Fehler, Angela Kessler, Gerhard Noebauer, Petteri Palm
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Publication number: 20220367350Abstract: In an embodiment, a semiconductor package includes a semiconductor device embedded in an insulating layer and having a first contact pad at a first surface of the semiconductor device. An outer contact pad is positioned on a lower surface of the insulating layer. A vertical redistribution structure electrically couples the first contact pad to the outer contact pad. The first contact pad has a plurality of first via sites. A first subset of the first via sites is occupied by first vias and a second subset of the first via sites remains unoccupied and forms a first via-free zone, such that the first vias are non-uniformly distributed over the first contact pad.Type: ApplicationFiled: July 29, 2022Publication date: November 17, 2022Inventors: Sergey Yuferev, Robert Fehler, Petteri Palm
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Patent number: 11469164Abstract: A packaged half-bridge circuit includes a carrier having a dielectric core and a first layer of metallization formed on an upper surface of the carrier, first and second semiconductor chips, each including a first terminal, a second terminal, and a control terminal, and a conductive connector mounted on the upper surface of the carrier and electrically connected to the first layer of metallization. The first semiconductor chip is configured as a high-side switch of the half-bridge circuit. The second semiconductor chip is configured as a low-side switch of the half-bridge circuit. At least one of the first and second semiconductor chips is embedded within the dielectric core of the carrier. The conductive connector is electrically connected to one of the first and second terminals from one or both of the first and second semiconductor chips.Type: GrantFiled: January 16, 2020Date of Patent: October 11, 2022Assignee: Infineon Technologies AGInventors: Robert Fehler, Eung San Cho, Danny Clavette, Petteri Palm
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Patent number: 11444017Abstract: In an embodiment, a semiconductor package includes a semiconductor device embedded in an insulating layer, a contact pad having an area, and a vertical redistribution structure including substantially parallel vertical paths arranged in the insulating layer and extending perpendicular to the area of the contact pad. The substantially vertical paths are non-uniformly distributed over the area of the contact pad.Type: GrantFiled: September 4, 2019Date of Patent: September 13, 2022Assignee: Infineon Technologies Austria AGInventors: Sergey Yuferev, Robert Fehler, Petteri Palm
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Publication number: 20220262716Abstract: A semiconductor assembly includes an interposer that includes an insulating substrate, a plurality of upper contact pads on an upper surface of the substrate, and a plurality of lower contact pads on a lower surface of the substrate, a semiconductor package that includes a semiconductor die embedded within a package body and a plurality of package terminals exposed from the package body, a first passive electrical element that includes first and second terminals, a first electrical connection between the first terminal of the first passive electrical element and a first one of the lower contact pads via the interposer, a second electrical connection between the second terminal of the first passive electrical element and a first one of the package terminals, and a third electrical connection between a second one of the package terminals and a second one of the lower contact pads via the interposer.Type: ApplicationFiled: February 16, 2021Publication date: August 18, 2022Inventors: Angela Kessler, Robert Carroll, Robert Fehler
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Patent number: 11348861Abstract: A semiconductor package includes a semiconductor die having a semiconductor device, and first and second contact pads arranged on opposite surfaces of the die. The semiconductor die is embedded in a dielectric layer. The semiconductor package also includes one or more first package contact pads and one or more second package contact pads arranged on a first major surface of the semiconductor package. The first contact pad of the die is coupled to the one or more first package contact pads, and the second contact pad of the die is coupled to the one or more second package contact pads. In operation, the semiconductor device causes a current path between the first contact pad and the second contact pad. The package contact pads are arranged on the first major surface of the semiconductor package to provide multiple non-parallel current paths.Type: GrantFiled: September 17, 2020Date of Patent: May 31, 2022Assignee: Infineon Technologies Austria AGInventors: Sergey Yuferev, Robert Fehler, Petteri Palm
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Publication number: 20220108945Abstract: A semiconductor module is provided that includes a low side switch, a high side switch and a control chip. The low side switch and the high side switch are arranged laterally adjacent one another and coupled by a switch node connector to form a half bridge circuit. The switch node connector includes two or more branches that have an arrangement with respect to the low side switch and to the high side switch and that each have a cross-sectional area. The arrangement and the cross-sectional area of the two or more branches are selected so as to homogenise the current density distribution within the switch node connector.Type: ApplicationFiled: October 5, 2021Publication date: April 7, 2022Inventors: Sergey Yuferev, Robert Fehler, Angela Kessler, Gerhard Noebauer, Petteri Palm
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Publication number: 20220028840Abstract: A circuitry is provided. The circuitry may include a power stage including a first transistor and a second transistor, an encapsulation including encapsulation material encapsulating the power stage, wherein the first transistor and the second transistor are arranged in an L-shape with respect to each other along their long axes, and a passive electronic component arranged on or embedded within the encapsulation at least partially, in top view, within a rectangular area defined by the L-shape configuration and further next to the first transistor and next to the second transistor.Type: ApplicationFiled: July 23, 2021Publication date: January 27, 2022Inventors: Robert Fehler, Sergey Yuferev
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Publication number: 20210287964Abstract: A semiconductor device is disclosed. In one example, the semiconductor device includes a semiconductor chip including a first chip contact pad on a first chip main surface. The semiconductor device further includes a first electrically conductive layer arranged over the first chip main surface and electrically coupled to the first chip contact pad, wherein the first electrically conductive layer extends in a direction parallel to the first chip main surface. An electrical through connection is electrically coupled to the first electrically conductive layer and to a second electrically conductive layer, wherein the electrical through connection extends in a direction perpendicular to the first chip main surface, and wherein, in a top view of the first chip main surface, the electrical through connection and the semiconductor chip are non-overlapping.Type: ApplicationFiled: March 9, 2021Publication date: September 16, 2021Applicant: Infineon Technologies AGInventors: Petteri PALM, Robert FEHLER, Josef HOEGLAUER, Angela KESSLER
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Publication number: 20210225745Abstract: A packaged half-bridge circuit includes a carrier having a dielectric core and a first layer of metallization formed on an upper surface of the carrier, first and second semiconductor chips, each including a first terminal, a second terminal, and a control terminal, and a conductive connector mounted on the upper surface of the carrier and electrically connected to the first layer of metallization. The first semiconductor chip is configured as a high-side switch of the half-bridge circuit. The second semiconductor chip is configured as a low-side switch of the half-bridge circuit. At least one of the first and second semiconductor chips is embedded within the dielectric core of the carrier. The conductive connector is electrically connected to one of the first and second terminals from one or both of the first and second semiconductor chips.Type: ApplicationFiled: January 16, 2020Publication date: July 22, 2021Inventors: Robert Fehler, Eung San Cho, Danny Clavette, Petteri Palm
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Patent number: 10916484Abstract: An electronic device is disclosed. In one example, the electronic device includes a solder ball, a dielectric layer comprising an opening, and a redistribution layer (RDL) comprising an RDL pad connected with the solder ball. The RDL pad including at least one void, the void being disposed at least in partial in an area of the RDL pad laterally outside of the opening of the dielectric layer.Type: GrantFiled: June 21, 2018Date of Patent: February 9, 2021Assignee: Infineon Technologies AGInventors: Robert Fehler, Francesca Arcioni, Christian Geissler, Walter Hartner, Gerhard Haubner, Thorsten Meyer, Martin Richard Niessner, Maciej Wojnowski
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Publication number: 20210005536Abstract: A semiconductor package includes a semiconductor die having a semiconductor device, and first and second contact pads arranged on opposite surfaces of the die. The semiconductor die is embedded in a dielectric layer. The semiconductor package also includes one or more first package contact pads and one or more second package contact pads arranged on a first major surface of the semiconductor package. The first contact pad of the die is coupled to the one or more first package contact pads, and the second contact pad of the die is coupled to the one or more second package contact pads. In operation, the semiconductor device causes a current path between the first contact pad and the second contact pad. The package contact pads are arranged on the first major surface of the semiconductor package to provide multiple non-parallel current paths.Type: ApplicationFiled: September 17, 2020Publication date: January 7, 2021Inventors: Sergey Yuferev, Robert Fehler, Petteri Palm
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Patent number: 10811342Abstract: A semiconductor package includes a semiconductor die having a semiconductor device, and first and second contact pads arranged on opposite surfaces of the die. The semiconductor die is embedded in a dielectric layer. The semiconductor package also includes one or more first package contact pads and one or more second package contact pads arranged on a first major surface of the semiconductor package. The first contact pad of the die is coupled to the one or more first package contact pads, and the second contact pad of the die is coupled to the one or more second package contact pads. In operation, the semiconductor device causes a current path between the first contact pad and the second contact pad. The package contact pads are arranged on the first major surface of the semiconductor package to provide multiple non-parallel current paths.Type: GrantFiled: February 27, 2019Date of Patent: October 20, 2020Assignee: Infineon Technologies Austria AGInventors: Sergey Yuferev, Robert Fehler, Petteri Palm
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Publication number: 20200075484Abstract: In an embodiment, a semiconductor package includes a semiconductor device embedded in an insulating layer, a contact pad having an area, and a vertical redistribution structure including substantially parallel vertical paths arranged in the insulating layer and extending perpendicular to the area of the contact pad. The substantially vertical paths are non-uniformly distributed over the area of the contact pad.Type: ApplicationFiled: September 4, 2019Publication date: March 5, 2020Inventors: Sergey Yuferev, Robert Fehler, Petteri Palm
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Publication number: 20190267309Abstract: A semiconductor package includes a semiconductor die having a semiconductor device, and first and second contact pads arranged on opposite surfaces of the die. The semiconductor die is embedded in a dielectric layer. The semiconductor package also includes one or more first package contact pads and one or more second package contact pads arranged on a first major surface of the semiconductor package. The first contact pad of the die is coupled to the one or more first package contact pads, and the second contact pad of the die is coupled to the one or more second package contact pads. In operation, the semiconductor device causes a current path between the first contact pad and the second contact pad. The package contact pads are arranged on the first major surface of the semiconductor package to provide multiple non-parallel current paths.Type: ApplicationFiled: February 27, 2019Publication date: August 29, 2019Inventors: Sergey Yuferev, Robert Fehler, Petteri Palm
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Publication number: 20180374769Abstract: An electronic device is disclosed. In one example, the electronic device includes a solder ball, a dielectric layer comprising an opening, and a redistribution layer (RDL) comprising an RDL pad connected with the solder ball. The RDL pad including at least one void, the void being disposed at least in partial in an area of the RDL pad laterally outside of the opening of the dielectric layer.Type: ApplicationFiled: June 21, 2018Publication date: December 27, 2018Applicant: Infineon Technologies AGInventors: Robert Fehler, Francesca Arcioni, Christian Geissler, Walter Hartner, Gerhard Haubner, Thorsten Meyer, Martin Richard Niessner, Maciej Wojnowski