Patents by Inventor Robert France
Robert France has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240099934Abstract: A wearable haptic navigation system for obscured visibility environments, the wearable haptic navigation system including: a wearable haptic component, in one alternative a body covering suite; and a mapping data collector and processor in communication with the wearable haptic component; wherein the mapping data collector and processor collects data related to a path traversed by a user of the wearable haptic navigation system and generates at least one proprioception suggestion signal to the wearable haptic component providing the user with a suggested safe egress path and/or a suggested safe body position.Type: ApplicationFiled: November 17, 2023Publication date: March 28, 2024Inventors: Brodie Myles Stanfield, Michael Gerald Stanfield, Alexander Ferworn, James Elliott Coleshill, Cassandra Frances Laffan, Robert Kozin
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Publication number: 20240071230Abstract: Described herein are examples of a computerized method that comprises: in response to obtaining information regarding a potential collision between a vehicle and an object, obtaining data describing the vehicle for a time period extending before and after a time of the potential collision. The method may determine a likelihood that the potential collision is a non-collision event based on the data describing the vehicle by performing one or more assessments. The assessments may include telematics monitor assessment, driver behavior assessment, road surface feature assessment, trip correlation assessment, and/or context assessment. In response to determining that the likelihood indicates that the potential collision is not a non-collision event, the method may trigger one or more actions responding to the potential collision.Type: ApplicationFiled: November 8, 2023Publication date: February 29, 2024Applicant: Geotab Inc.Inventors: Willem Petersen, Harjot Singh Parmar, Amish Vijay Patel, Meghan Frances Fotak, Paul Stobbe, Robert Spencer Hockin
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Publication number: 20230401147Abstract: Methods that can facilitate more optimized relocation of data associated with a memory are presented. In addition to a memory controller component, a memory manager component can be employed to increase available processing resources to facilitate more optimal execution of higher level functions. Higher level functions can be delegated to the memory manager component to allow execution of these higher level operations with reduced or no load on the memory controller component resources. A uni-bus or multi-bus architecture can be employed to further optimize data relocation operations. A first bus can be utilized for data access operations including read, write, erase, refresh, or combinations thereof, among others, while a second bus can be designated for higher level operations including data compaction, error code correction, wear leveling, or combinations thereof, among others.Type: ApplicationFiled: March 20, 2023Publication date: December 14, 2023Inventors: Walter Allen, Robert France
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Patent number: 11609847Abstract: Methods that can facilitate more optimized relocation of data associated with a memory are presented. In addition to a memory controller component, a memory manager component can be employed to increase available processing resources to facilitate more optimal execution of higher level functions. Higher level functions can be delegated to the memory manager component to allow execution of these higher level operations with reduced or no load on the memory controller component resources. A uni-bus or multi-bus architecture can be employed to further optimize data relocation operations. A first bus can be utilized for data access operations including read, write, erase, refresh, or combinations thereof, among others, while a second bus can be designated for higher level operations including data compaction, error code correction, wear leveling, or combinations thereof, among others.Type: GrantFiled: August 16, 2021Date of Patent: March 21, 2023Assignee: MONTEREY RESEARCH, LLCInventors: Walter Allen, Robert France
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Publication number: 20210374052Abstract: Methods that can facilitate more optimized relocation of data associated with a memory are presented. In addition to a memory controller component, a memory manager component can be employed to increase available processing resources to facilitate more optimal execution of higher level functions. Higher level functions can be delegated to the memory manager component to allow execution of these higher level operations with reduced or no load on the memory controller component resources. A uni-bus or multi-bus architecture can be employed to further optimize data relocation operations. A first bus can be utilized for data access operations including read, write, erase, refresh, or combinations thereof, among others, while a second bus can be designated for higher level operations including data compaction, error code correction, wear leveling, or combinations thereof, among others.Type: ApplicationFiled: August 16, 2021Publication date: December 2, 2021Inventors: Walter Allen, Robert France
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Patent number: 11093383Abstract: Methods that can facilitate more optimized relocation of data associated with a memory are presented. In addition to a memory controller component, a memory manager component can be employed to increase available processing resources to facilitate more optimal execution of higher level functions. Higher level functions can be delegated to the memory manager component to allow execution of these higher level operations with reduced or no load on the memory controller component resources. A uni-bus or multi-bus architecture can be employed to further optimize data relocation operations. A first bus can be utilized for data access operations including read, write, erase, refresh, or combinations thereof, among others, while a second bus can be designated for higher level operations including data compaction, error code correction, wear leveling, or combinations thereof, among others.Type: GrantFiled: February 11, 2019Date of Patent: August 17, 2021Assignee: MONTEREY RESEARCH, LLCInventors: Walter Allen, Robert France
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Publication number: 20190171562Abstract: Methods that can facilitate more optimized relocation of data associated with a memory are presented. In addition to a memory controller component, a memory manager component can be employed to increase available processing resources to facilitate more optimal execution of higher level functions. Higher level functions can be delegated to the memory manager component to allow execution of these higher level operations with reduced or no load on the memory controller component resources. A uni-bus or multi-bus architecture can be employed to further optimize data relocation operations. A first bus can be utilized for data access operations including read, write, erase, refresh, or combinations thereof, among others, while a second bus can be designated for higher level operations including data compaction, error code correction, wear leveling, or combinations thereof, among others.Type: ApplicationFiled: February 11, 2019Publication date: June 6, 2019Inventors: Walter Allen, Robert France
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Patent number: 10204041Abstract: Methods that can facilitate more optimized relocation of data associated with a memory are presented. In addition to a memory controller component, a memory manager component can be employed to increase available processing resources to facilitate more optimal execution of higher level functions. Higher level functions can be delegated to the memory manager component to allow execution of these higher level operations with reduced or no load on the memory controller component resources. A uni-bus or multi-bus architecture can be employed to further optimize data relocation operations. A first bus can be utilized for data access operations including read, write, erase, refresh, or combinations thereof, among others, while a second bus can be designated for higher level operations including data compaction, error code correction, wear leveling, or combinations thereof, among others.Type: GrantFiled: August 14, 2017Date of Patent: February 12, 2019Assignee: Monterey Research, LLCInventors: Walter Allen, Robert France
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Publication number: 20180137046Abstract: Methods that can facilitate more optimized relocation of data associated with a memory are presented. In addition to a memory controller component, a memory manager component can be employed to increase available processing resources to facilitate more optimal execution of higher level functions. Higher level functions can be delegated to the memory manager component to allow execution of these higher level operations with reduced or no load on the memory controller component resources. A uni-bus or multi-bus architecture can be employed to further optimize data relocation operations. A first bus can be utilized for data access operations including read, write, erase, refresh, or combinations thereof, among others, while a second bus can be designated for higher level operations including data compaction, error code correction, wear leveling, or combinations thereof, among others.Type: ApplicationFiled: August 14, 2017Publication date: May 17, 2018Inventors: Walter Allen, Robert France
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Patent number: 9734049Abstract: Methods that can facilitate more optimized relocation of data associated with a memory are presented. In addition to a memory controller component, a memory manager component can be employed to increase available processing resources to facilitate more optimal execution of higher level functions. Higher level functions can be delegated to the memory manager component to allow execution of these higher level operations with reduced or no load on the memory controller component resources. A uni-bus or multi-bus architecture can be employed to further optimize data relocation operations. A first bus can be utilized for data access operations including read, write, erase, refresh, or combinations thereof, among others, while a second bus can be designated for higher level operations including data compaction, error code correction, wear leveling, or combinations thereof, among others.Type: GrantFiled: July 2, 2012Date of Patent: August 15, 2017Assignee: MONTEREY RESEARCH, LLCInventors: Walter Allen, Robert France
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Patent number: 8555733Abstract: A system for preparing a refrigerant sample for analysis including a pressure regulator assembly including a pressure regulator and provisions for heating a refrigerant sample contained within an interior region of the pressure regulator. The pressure regulator defines an inlet through which the refrigerant sample is delivered and an outlet through which the refrigerant sample is expelled. The system also includes a filter assembly having an inlet that is fluidly connected to the outlet of the pressure regulator to receive the vaporized refrigerant sample from the pressure regulator, at least one filter for removing contaminants from the refrigerant sample, and an outlet that is configured to be coupled to a refrigerant analysis system for analyzing a composition of the refrigerant sample.Type: GrantFiled: September 23, 2011Date of Patent: October 15, 2013Assignee: Airgas, Inc.Inventors: Robert Frances Shock, James Gruenbacher, Maciej Kuchcinski, Alexey Virovets
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Patent number: 8464021Abstract: Systems and/or methods that facilitate logical block address (LBA) to physical block address (PBA) translations associated with a memory component(s) are presented. The disclosed subject matter employs an optimized block address (BA) component that can facilitate caching the LBA to PBA translations within a memory controller component based in part on a predetermined optimization criteria to facilitate improving the access of data associated with the memory component. The predetermined optimization criteria can relate to a length of time since an LBA has been accessed, a number of times the LBA has been access, a data size of data related to an LBA, and/or other factors. The LBA to PBA translations can be utilized to facilitate accessing the LBA and/or associated data using the cached translation, instead of performing various functions to determine the translation.Type: GrantFiled: May 28, 2008Date of Patent: June 11, 2013Assignee: Spansion LLCInventors: Walter Allen, Sunil Atri, Robert France
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Publication number: 20130074611Abstract: A system for preparing a refrigerant sample for analysis including a pressure regulator assembly including a pressure regulator and provisions for heating a refrigerant sample contained within an interior region of the pressure regulator. The pressure regulator defines an inlet through which the refrigerant sample is delivered and an outlet through which the refrigerant sample is expelled. The system also includes a filter assembly having an inlet that is fluidly connected to the outlet of the pressure regulator to receive the vaporized refrigerant sample from the pressure regulator, at least one filter for removing contaminants from the refrigerant sample, and an outlet that is configured to be coupled to a refrigerant analysis system for analyzing a composition of the refrigerant sample.Type: ApplicationFiled: September 23, 2011Publication date: March 28, 2013Applicant: Airgas, Inc.Inventors: Robert Frances Shock, James Gruenbacher, Maciej Kuchcinski, Alexey Virovets
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Publication number: 20120271991Abstract: Methods that can facilitate more optimized relocation of data associated with a memory are presented. In addition to a memory controller component, a memory manager component can be employed to increase available processing resources to facilitate more optimal execution of higher level functions. Higher level functions can be delegated to the memory manager component to allow execution of these higher level operations with reduced or no load on the memory controller component resources. A uni-bus or multi-bus architecture can be employed to further optimize data relocation operations. A first bus can be utilized for data access operations including read, write, erase, refresh, or combinations thereof, among others, while a second bus can be designated for higher level operations including data compaction, error code correction, wear leveling, or combinations thereof, among others.Type: ApplicationFiled: July 2, 2012Publication date: October 25, 2012Applicant: SPANSION LLCInventors: Walter Allen, Robert France
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Patent number: 8239611Abstract: Systems and methods that can facilitate more optimized relocation of data associated with a memory are presented. In addition to a memory controller component, a memory manager component can be employed to increase available processing resources to facilitate more optimal execution of higher level functions. Higher level functions can be delegated to the memory manager component to allow execution of these higher level operations with reduced or no load on the memory controller component resources. A uni-bus or multi-bus architecture can be employed to further optimize data relocation operations. A first bus can be utilized for data access operations including read, write, erase, refresh, or combinations thereof, among others, while a second bus can be designated for higher level operations including data compaction, error code correction, wear leveling, or combinations thereof, among others.Type: GrantFiled: December 28, 2007Date of Patent: August 7, 2012Assignee: Spansion LLCInventors: Walter Allen, Robert France
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Publication number: 20110184771Abstract: A method and apparatus provides management of projects including breaking the project into tasks and task dependencies and assigning employees as resources to work on the task dependencies. Resources are evaluated based on skills, experience with applications, distance to work site, customer satisfaction rating of prior work and availability. Progress on the project is monitored by input of employee time into the system. Projected completion dates, start dates of subsequent projects and resource allocation is automatically determined as changes in project progress and resources occur.Type: ApplicationFiled: December 21, 2010Publication date: July 28, 2011Inventor: Robert Frances WELLS
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Patent number: 7979667Abstract: Systems and/or methods that facilitate a search of a memory component(s) to locate a desired logical block address (LBA) associated with a memory location in a memory component are presented. Searches to locate a desired LBA(s) in a memory component(s) associated with a processor component are offloaded and controlled by the memory component(s). A search component searches pages in the memory array to facilitate locating a page of data associated with an LBA stored in the memory component. The search component can retrieve a portion of a page of data in a block in the memory component to facilitate determining whether the page contains an LBA associated with a command based in part on command information. The search component can search pages in the memory component until a desired page is located or a predetermined number of searches is performed without locating the desired page.Type: GrantFiled: December 10, 2007Date of Patent: July 12, 2011Assignee: Spansion LLCInventors: Walter Allen, Robert France
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Patent number: 7949851Abstract: Systems and/or methods that facilitate PBA and LBA translations associated with a memory component(s) are presented. A memory controller component facilitates determining which memory component, erase block, page, and data block contains a PBA in which a desired LBA and/or associated data is stored. The memory controller component facilitates control of performance of calculation functions, table look-up functions, and/or search functions to locate the desired LBA. The memory controller component generates a configuration sequence based in part on predefined optimization criteria to facilitate optimized performance of translations. The memory controller component and/or associated memory component(s) can be configured so that the translation attributes are determined in a desired order using the desired translation function(s) to determine a respective translation attribute based in part on the predefined optimization criteria. The LBA to PBA translations can be performed in parallel by memory components.Type: GrantFiled: December 28, 2007Date of Patent: May 24, 2011Assignee: Spansion LLCInventors: Walter Allen, Sunil Atri, Robert France
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Patent number: 7675776Abstract: Systems and methods that facilitate bad block management in a memory device that comprises nonvolatile memory are presented. One or more memory blocks of a memory device are each associated with one or more additional, dedicated bits that facilitate indicating whether the associated memory block is defective. These additional bits, called bad block bits, can be stored in a hardware-based storage mechanism within the memory device. Once a defect is detected in a memory block, at least one of the associated bad block bits can be set to indicate that the memory block is defective. If at least one of the bad block bits associated with a memory block indicates a memory block is defective, access to the memory block can be prevented.Type: GrantFiled: December 21, 2007Date of Patent: March 9, 2010Assignee: Spansion, LLCInventors: Walter Allen, Robert France, Sunil Atri
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Publication number: 20090300318Abstract: Systems and/or methods that facilitate logical block address (LBA) to physical block address (PBA) translations associated with a memory component(s) are presented. The disclosed subject matter employs an optimized block address (BA) component that can facilitate caching the LBA to PBA translations within a memory controller component based in part on a predetermined optimization criteria to facilitate improving the access of data associated with the memory component. The predetermined optimization criteria can relate to a length of time since an LBA has been accessed, a number of times the LBA has been access, a data size of data related to an LBA, and/or other factors. The LBA to PBA translations can be utilized to facilitate accessing the LBA and/or associated data using the cached translation, instead of performing various functions to determine the translation.Type: ApplicationFiled: May 28, 2008Publication date: December 3, 2009Applicant: SPANSION LLCInventors: Walter Allen, Sunil Atri, Robert France