Abstract: A method of, and apparatus for, decoupling a defective or otherwise non-operational memory block from the power lines of a memory device is disclosed. Defects which cause excessive current consumption in defective memory blocks can be repaired through this approach. Mass-production yields can be improved significantly.

Abstract: A self-aligned multi-level interconnect structure and a method for fabricating the same are disclosed. The multi-level interconnect structure is fabricated by the steps of: (1) forming a first plurality of spaced-apart insulative layers [231-233], where the first plurality includes a top insulative layer [233]; (2) forming a second plurality of spaced-apart conductors [221,222] and positioning them interdigitally between the insulative layers; (3) defining a first hole [233h] extending through the top insulative layer [233]; (4) using the first hole [233h] to define a succession of self-aligned subsequent holes [222h,232h,22ih,231h] through the underlying conductors and insulative layers, each successive hole being continuous with and self-aligned to one above it; and (5) defining a through-conductor [223] extending through the succession of self-aligned holes. The self-aligned multi-level interconnect structure is employed in a multi-layer SRAM cell.

Abstract: A method of, and apparatus for, decoupling a defective or otherwise non-operational memory block from the power lines of a memory device is disclosed. Defects which cause excessive current consumption in defective memory blocks can be repaired through this approach. Mass-production yields can be improved significantly.

Abstract: A reference circuit which is particularly useful in combination with a memory array in which data transistors are arranged in rows and columns and in which the conduction paths of the data transistors along each column are connected in series between a common ground line and a bit line forming a stack. A problem exists in that the signal current flowing in a stack varies as a function of the position of a selected data transistor along the stack and of the information stored in the other data transistors of the stack. The reference circuit includes means for generating a different reference current corresponding to each row of data transistors along the stacks, where each reference current mirrors and tracks a particular signal condition of the data transistors being sensed in its corresponding row.

Abstract: A programmable buffer settable by means of control signals to function either as: (a) an inverting buffer; (b) a non-inverting buffer; or (c) to produce a fixed output level independent of the value of its input signal.

Abstract: A first insulated-gate field-effect transistor (IGFET), responsive to an input voltage, supplies a current to a second IGFET when the input voltage exceeds the threshold voltage of the first IGFET. The second IGFET is connected in combination with a third IGFET, of complementary conductivity type, for sensing when the input voltage exceeds the sum of the threshold voltages of the second and third IGFETs. When that occurs, the third IGFET produces an output which is fed back to the first IGFET interrupting the flow of current between the first and second IGFETs.