Patents by Inventor Robert GITERMAN
Robert GITERMAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240159601Abstract: A Mass Flow Sensor (MFS) is provided and includes an MFS housing, a mounting structure, having a mounting structure top and a mounting structure bottom, wherein the MFS housing is associated with the mounting structure top, a first sensor leg, wherein the first sensor leg extends away from the mounting structure bottom and includes a first temperature measurement device and a heating element. The MFS further includes a second sensor leg, wherein the second sensor leg extends away from the mounting structure and includes a second temperature measurement device and an airfoil structure, wherein the airfoil structure defines an airfoil cavity and is associated with the mounting structure bottom to contain the first sensor leg and the second sensor leg.Type: ApplicationFiled: November 14, 2023Publication date: May 16, 2024Applicant: HarcoSemco LLCInventors: Igor Giterman, Robert A. Croce, JR.
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Publication number: 20240062811Abstract: A fin field-effect transistor (FinFET) based semiconductor memory array having a plurality of memory cells, each memory cell including a write transistor having a write wordline gate over a first fin connected to a write wordline gate contact, a write bitline contact in connection with the first fin, and a storage node contact in connection with the first fin, and a read transistor having a storage node gate over a second fin, the storage node gate connected to a storage node gate contact, the storage node gate contact connected to the storage node contact, a read wordline contact in connection with the second fin, and a read bitline contact in connection with the second fin, wherein the write wordline gate and the storage node gate are arranged in series to each other along an extension axis that coincides with an longitudinal axis of the write wordline gate and a longitudinal axis of the storage node gate.Type: ApplicationFiled: August 18, 2022Publication date: February 22, 2024Inventors: Robert Giterman, Andreas Burg, Halil Andac Yigit
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Patent number: 11586778Abstract: A hardware memory includes at least one memory cell, peripheral circuitry and randomization circuitry. The memory cell(s) store data, which may be written to, read from and held in the hardware memory. The peripheral circuitry reads and writes data to the memory cell(s) and may perform other functions necessary for facilitating the data read, write and hold. The randomization circuitry randomizes operations performed by the peripheral circuitry to reduce a correlation between the data and the current consumed by the hardware memory.Type: GrantFiled: December 6, 2018Date of Patent: February 21, 2023Assignee: Bar-Ilan UniversityInventors: Robert Giterman, Itamar Levi, Yoav Weizman, Osnat Keren, Alexander Fish, Maoz Vizentovski
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Patent number: 11309008Abstract: An FD-SOI GC-edRAM gain cell includes: a write bit line terminal connected to a WBL; a read bit line terminal connected to a RBL; a write trigger terminal connected to a WWL, for inputting a write trigger signal; a read trigger terminal put connected to a RWL, for inputting a read trigger signal; at least one body voltage terminal connected to a respective body voltage; and multiple FD-SOI transistors. The FD-SOI transistors are interconnected to form a storage node for retaining a data signal. The bodies of at least two of the transistors are coupled in a single well to a body voltage terminal. The write trigger signal triggers writing an input data signal from the write bit line terminal to the storage node and the read trigger signal triggers outputting the retained data signal from the storage node to the read bit line terminal.Type: GrantFiled: July 9, 2019Date of Patent: April 19, 2022Assignee: Bar-Ilan UniversityInventors: Robert Giterman, Adam Teman
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Patent number: 11127455Abstract: A FinFET gain cell includes a write port, read port and storage node. The write port includes at least one write FinFET transistor and has write word-line (WWL) and write bit-line (WBL) inputs. The read port includes at least one FinFET read transistor and has a read word-line (RWL) input and a read bit-line (RBL) output. The storage node stores a data level written from said WBL. The storage nodes includes a single layer interconnect which connects the write port output diffusion connection to the read port input gate connection. The height of the single layer interconnect at the write port output diffusion connection is different from the height of the single layer interconnect at the read port input gate connection.Type: GrantFiled: November 28, 2019Date of Patent: September 21, 2021Assignee: Bar-Ilan UniversityInventors: Adam Teman, Amir Shalom, Robert Giterman, Alexander Fish
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Publication number: 20210272616Abstract: An FD-SOI GC-edRAM gain cell includes: a write bit line terminal connected to a WBL; a read bit line terminal connected to a RBL; a write trigger terminal connected to a WWL, for inputting a write trigger signal; a read trigger terminal put connected to a RWL, for inputting a read trigger signal; at least one body voltage terminal connected to a respective body voltage; and multiple FD-SOI transistors. The FD-SOI transistors are interconnected to form a storage node for retaining a data signal. The bodies of at least two of the transistors are coupled in a single well to a body voltage terminal. The write trigger signal triggers writing an input data signal from the write bit line terminal to the storage node and the read trigger signal triggers outputting the retained data signal from the storage node to the read bit line terminal.Type: ApplicationFiled: July 9, 2019Publication date: September 2, 2021Applicant: Bar-Ilan UniversityInventors: Robert GITERMAN, Adam TEMAN
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Publication number: 20210166751Abstract: A FinFET gain cell includes a write port, read port and storage node. The write port includes at least one write FinFET transistor and has write word-line (WWL) and write bit-line (WBL) inputs. The read port includes at least one FinFET read transistor and has a read word-line (RWL) input and a read bit-line (RBL) output. The storage node stores a data level written from said WBL. The storage nodes includes a single layer interconnect which connects the write port output diffusion connection to the read port input gate connection. The height of the single layer interconnect at the write port output diffusion connection is different from the height of the single layer interconnect at the read port input gate connection.Type: ApplicationFiled: November 28, 2019Publication date: June 3, 2021Applicant: Bar-Ilan UniversityInventors: Adam TEMAN, Amir SHALOM, Robert GITERMAN, Alexander FISH
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Patent number: 10991421Abstract: A CDMR memory cell, includes a first bitcell which is used to store a current data level and a second bitcell which is used to store the complementary data level. When a read operation is performed, a comparator compares the data levels read from the two bitcells. If these two levels are not complementary, the comparator outputs an indicator. This indicator serves as an alert that a storage error has, or may have, occurred.Type: GrantFiled: September 19, 2017Date of Patent: April 27, 2021Assignee: Bar-Ilan UniversityInventors: Robert Giterman, Lior Atias, Adam Teman, Alexander Fish
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Publication number: 20200372186Abstract: A hardware memory includes at least one memory cell, peripheral circuitry and randomization circuitry. The memory cell(s) store data, which may be written to, read from and held in the hardware memory. The peripheral circuitry reads and writes data to the memory cell(s) and may perform other functions necessary for facilitating the data read, write and hold. The randomization circuitry randomizes operations performed by the peripheral circuitry to reduce a correlation between the data and the current consumed by the hardware memory.Type: ApplicationFiled: December 6, 2018Publication date: November 26, 2020Applicant: Bar-Ilan UniversityInventors: Robert GITERMAN, Itamar LEVI, Yoav WEIZMAN, Osnat KEREN, Alexander FISH, Maoz VIZENTOVSKI
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Patent number: 10811073Abstract: A method uses data retention time (DRT) characteristics of a logic-compatible gain-cell embedded DRAM (dynamic random-access memory) (GC-eDRAM) array in a transistor circuit as a source for physical unclonable function (PUF) signature extraction of the circuit.Type: GrantFiled: April 18, 2019Date of Patent: October 20, 2020Assignee: Birad—Research & Development Company Ltd.Inventors: Robert Giterman, Yoav Weizman, Adam Teman
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Patent number: 10497410Abstract: A high-density memory includes: a data write interface, a data read interface, an array of memory cells and level-shifting write drivers. The data write interface inputs data written to the memory. The data read interface outputs data read from the memory. The array of memory cells stores data input at the data write interface and outputs stored data to the data read interface. Each of the memory cells includes at least one low threshold voltage (LVT) read transistor and at least one respective regular threshold voltage (RVT) transistor, so as to obtain high-speed read operations. The level-shifting write drivers supply shifted write wordline voltages to the array, so as to obtain high-speed write operations.Type: GrantFiled: September 5, 2018Date of Patent: December 3, 2019Assignees: MELLANOX TECHNOLOGIES, LTD., BAR-ILAN UNIVERSITYInventors: Elad Mentovich, Narkis Geuli, Robert Giterman, Alexander Fish, Adam Teman
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Publication number: 20190333567Abstract: A method uses data retention time (DRT) characteristics of a logic-compatible gain-cell embedded DRAM (dynamic random-access memory) (GC-eDRAM) array in a transistor circuit as a source for physical unclonable function (PUF) signature extraction of the circuit.Type: ApplicationFiled: April 18, 2019Publication date: October 31, 2019Applicant: Birad - Research & Development Company Ltd.Inventors: Robert Giterman, Yoav Weizman, Adam Teman
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Publication number: 20190295633Abstract: A CDMR memory cell, includes a first bitcell which is used to store a current data level and a second bitcell which is used to store the complementary data level. When a read operation is performed, a comparator compares the data levels read from the two bitcells. If these two levels are not complementary, the comparator outputs an indicator. This indicator serves as an alert that a storage error has, or may have, occurred.Type: ApplicationFiled: September 19, 2017Publication date: September 26, 2019Applicant: Bar-llan UniversityInventors: Robert GITERMAN, Lior ATIAS, Adam TEMAN, Alexander FISH
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Publication number: 20190074040Abstract: A high-density memory includes: a data write interface, a data read interface, an array of memory cells and level-shifting write drivers. The data write interface inputs data written to the memory. The data read interface outputs data read from the memory. The array of memory cells stores data input at the data write interface and outputs stored data to the data read interface. Each of the memory cells includes at least one low threshold voltage (LVT) read transistor and at least one respective regular threshold voltage (RVT) transistor, so as to obtain high-speed read operations. The level-shifting write drivers supply shifted write wordline voltages to the array, so as to obtain high-speed write operations.Type: ApplicationFiled: September 5, 2018Publication date: March 7, 2019Inventors: Elad Mentovich, Narkis Geuli, Robert Giterman, Alexander Fish, Adam Teman
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Patent number: 10002660Abstract: A gain cell includes a write bit line input, a read bit line output, a write trigger input and a read trigger input. The write element writes a data level from the write bit line input to the gain cell when triggered by the write trigger input. The retention element buffers between an internal buffer node and an internal storage node during data retention. The retention element also connects or disconnects the buffer node to a first constant voltage according to the data level being retained in the gain cell. The read element decouples the storage node from the read bit line output during data read. The read element also connects and disconnects the read bit line output to a second constant voltage according to the data level being read from the gain cell.Type: GrantFiled: June 26, 2017Date of Patent: June 19, 2018Assignee: Bar-Ilan UniversityInventors: Robert Giterman, Adam Teman, Pascal Meinerzhagen, Andreas Burg, Alexander Fish
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Publication number: 20170294221Abstract: A gain cell includes a write bit line input, a read bit line output, a write trigger input and a read trigger input. The write element writes a data level from the write bit line input to the gain cell when triggered by the write trigger input. The retention element buffers between an internal buffer node and an internal storage node during data retention. The retention element also connects or disconnects the buffer node to a first constant voltage according to the data level being retained in the gain cell. The read element decouples the storage node from the read bit line output during data read. The read element also connects and disconnects the read bit line output to a second constant voltage according to the data level being read from the gain cell.Type: ApplicationFiled: June 26, 2017Publication date: October 12, 2017Inventors: Robert GITERMAN, Adam Teman, Pascal Meinerzhagen, Andreas Burg, Alexander Fish
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Patent number: 9691445Abstract: A gain cell includes a write bit line input, a read bit line output, a write trigger input and a read trigger input. The gain cell also includes a write transistor, retention element and read transistor. Each of the transistors includes a respective first diffusion connection, gate connection and second diffusion connection. The write transistor first diffusion connection is connected to the write bit line input and the write transistor gate connection is connected to the write trigger input. The read transistor first diffusion connection being connected to the read bit line output and the second diffusion connection is connected to the read trigger input. The retention element buffers between write transistor and the read transistor during data retention. The retention element also connects or disconnects a write transistor diffusion connection to/from a constant voltage in accordance with a retained data level at the read transistor gate connection.Type: GrantFiled: April 30, 2015Date of Patent: June 27, 2017Assignee: Bar-Ilan UniversityInventors: Robert Giterman, Adam Teman, Pascal Meinerzhagen, Andreas Burg, Alexander Fish
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Publication number: 20170062024Abstract: A gain cell includes a write bit line input, a read bit line output, a write trigger input and a read trigger input. The gain cell also includes a write transistor, retention element and read transistor. Each of the transistors includes a respective first diffusion connection, gate connection and second diffusion connection. The write transistor first diffusion connection is connected to the write bit line input and the write transistor gate connection is connected to the write trigger input. The read transistor first diffusion connection being connected to the read bit line output and the second diffusion connection is connected to the read trigger input. The retention element buffers between write transistor and the read transistor during data retention. The retention element also connects or disconnects a write transistor diffusion connection to/from a constant voltage in accordance with a retained data level at the read transistor gate connection.Type: ApplicationFiled: April 30, 2015Publication date: March 2, 2017Inventors: Robert GITERMAN, Adam TEMAN, Pascal MEINERZHAGEN, Andreas BURG, Alexander FISH