Patents by Inventor Robert Graham Isherwood
Robert Graham Isherwood has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9769489Abstract: Methods and encoders for tracing an error in a frame of a video to a subsequent frame of the video. In response to receiving an error notification message indicating an error has occurred in an encoded frame during decode, an encoder obtains: (a) the minimum and maximum horizontal motion vector components for each column of blocks of the frame immediately following the error frame; and (b) the minimum and maximum vertical motion vector components for each row of blocks of the frame immediately following the error frame. A rectangular region of blocks of the frame immediately following the error frame that the error is likely to have propagated to is identified using the minimum and maximum horizontal and vertical motion vector components.Type: GrantFiled: August 15, 2016Date of Patent: September 19, 2017Assignee: Imagination Technologies LimitedInventors: Sudhanshu Sohoni, Parag Salasakar, Robert Graham Isherwood
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Patent number: 9727380Abstract: Global register protection in a multi-threaded processor is described. In an embodiment, global resources within a multi-threaded processor are protected by performing checks, before allowing a thread to write to a global resource, to determine whether the thread has write access to the particular global resource. The check involves accessing one or more local control registers or a global control field within the multi-threaded processor and in an example, a local register associated with each other thread in the multi-threaded processor is accessed and checked to see whether it contains an identifier for the particular global resource. Only if none of the accessed local resources contain such an identifier, is the instruction issued and the thread allowed to write to the global resource. Otherwise, the instruction is blocked and an exception may be raised to alert the program that issued the instruction that the write failed.Type: GrantFiled: February 19, 2015Date of Patent: August 8, 2017Assignee: Imagination Technologies LimitedInventors: Guixin Wang, Hugh Jackson, Robert Graham Isherwood
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Patent number: 9720695Abstract: The invention is a method and system for providing trace data in a pipelined data processor. Aspects of the invention include providing a trace pipeline in parallel to the execution pipeline, providing trace information on whether conditional instructions complete or not, providing trace information on the interrupt status of the processor, replacing instructions in the processor with functionally equivalent instructions that also produce trace information and modifying the scheduling of instructions in the processor based on the occupancy of a trace output buffer.Type: GrantFiled: May 7, 2014Date of Patent: August 1, 2017Assignee: Imagination Technologies LimitedInventors: Robert Graham Isherwood, Ian Oliver, Andrew David Webber
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Patent number: 9703709Abstract: A multithreaded processor can concurrently execute a plurality of threads in a processor core. The threads can access a shared main memory through a memory interface; the threads can generate read and write transactions that cause shared main memory access. An incoherency detection module prevents incoherency by maintaining a record of outstanding global writes, and detecting a conflicting global read. A barrier is sequenced with the conflicting global write. The conflicting global read is allowed to proceed after the sequence of the conflicting global write and the barrier are cleared. The sequence can be maintained by a separate queue for each thread of the plurality.Type: GrantFiled: July 6, 2015Date of Patent: July 11, 2017Assignee: Imagination Technologies LimitedInventors: Robert Graham Isherwood, Yin Nam Ko
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Publication number: 20160353126Abstract: Methods and encoders for tracing an error in a frame of a video to a subsequent frame of the video. In response to receiving an error notification message indicating an error has occurred in an encoded frame during decode, an encoder obtains: (a) the minimum and maximum horizontal motion vector components for each column of blocks of the frame immediately following the error frame; and (b) the minimum and maximum vertical motion vector components for each row of blocks of the frame immediately following the error frame. A rectangular region of blocks of the frame immediately following the error frame that the error is likely to have propagated to is identified using the minimum and maximum horizontal and vertical motion vector components.Type: ApplicationFiled: August 15, 2016Publication date: December 1, 2016Inventors: Sudhanshu Sohoni, Parag Salasakar, Robert Graham Isherwood
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Patent number: 9445117Abstract: Methods and encoders for tracing an error in a frame of a video to a subsequent frame of the video. In response to receiving an error notification message indicating an error has occurred in an encoded frame during decode, an encoder obtains: (a) the minimum and maximum horizontal motion vector components for each column of blocks of the frame immediately following the error frame; and (b) the minimum and maximum vertical motion vector components for each row of blocks of the frame immediately following the error frame. A rectangular region of blocks of the frame immediately following the error frame that the error is likely to have propagated to is identified using the minimum and maximum horizontal and vertical motion vector components.Type: GrantFiled: March 12, 2015Date of Patent: September 13, 2016Assignee: Imagination Technologies LimitedInventors: Sudhanshu Sohoni, Parag Salasakar, Robert Graham Isherwood
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Publication number: 20160034395Abstract: A multithreaded processor can concurrently execute a plurality of threads in a processor core. The threads can access a shared main memory through a memory interface; the threads can generate read and write transactions that cause shared main memory access. An incoherency detection module prevents incoherency by maintaining a record of outstanding global writes, and detecting a conflicting global read. A barrier is sequenced with the conflicting global write. The conflicting global read is allowed to proceed after the sequence of the conflicting global write and the barrier are cleared. The sequence can be maintained by a separate queue for each thread of the plurality.Type: ApplicationFiled: July 6, 2015Publication date: February 4, 2016Inventors: Robert Graham Isherwood, Yin Nam Ko
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Publication number: 20150264391Abstract: Methods and encoders for tracing an error in a frame of a video to a subsequent frame of the video. In response to receiving an error notification message indicating an error has occurred in an encoded frame during decode, an encoder obtains: (a) the minimum and maximum horizontal motion vector components for each column of blocks of the frame immediately following the error frame; and (b) the minimum and maximum vertical motion vector components for each row of blocks of the frame immediately following the error frame. A rectangular region of blocks of the frame immediately following the error frame that the error is likely to have propagated to is identified using the minimum and maximum horizontal and vertical motion vector components.Type: ApplicationFiled: March 12, 2015Publication date: September 17, 2015Inventors: Sudhanshu Sohoni, Parag Salasakar, Robert Graham Isherwood
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Patent number: 9075724Abstract: A multithreaded processor can concurrently execute a plurality of threads in a processor core. The threads can access a shared main memory through a memory interface; the threads can generate read and write transactions that cause shared main memory access. An incoherency detection module prevents incoherency by maintaining a record of outstanding global writes, and detecting a conflicting global read. A barrier is sequenced with the conflicting global write. The conflicting global read is allowed to proceed after the sequence of the conflicting global write and the barrier are cleared. The sequence can be maintained by a separate queue for each thread of the plurality.Type: GrantFiled: July 23, 2012Date of Patent: July 7, 2015Assignee: Imagination Technologies LimitedInventors: Robert Graham Isherwood, Yin Nam Ko
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Publication number: 20150160981Abstract: Global register protection in a multi-threaded processor is described. In an embodiment, global resources within a multi-threaded processor are protected by performing checks, before allowing a thread to write to a global resource, to determine whether the thread has write access to the particular global resource. The check involves accessing one or more local control registers or a global control field within the multi-threaded processor and in an example, a local register associated with each other thread in the multi-threaded processor is accessed and checked to see whether it contains an identifier for the particular global resource. Only if none of the accessed local resources contain such an identifier, is the instruction issued and the thread allowed to write to the global resource. Otherwise, the instruction is blocked and an exception may be raised to alert the program that issued the instruction that the write failed.Type: ApplicationFiled: February 19, 2015Publication date: June 11, 2015Inventors: Guixin Wang, Hugh Jackson, Robert Graham Isherwood
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Patent number: 8996847Abstract: Global register protection in a multi-threaded processor is described. In an embodiment, global resources within a multi-threaded processor are protected by performing checks, before allowing a thread to write to a global resource, to determine whether the thread has write access to the particular global resource. The check involves accessing one or more local control registers or a global control field within the multi-threaded processor and in an example, a local register associated with each other thread in the multi-threaded processor is accessed and checked to see whether it contains an identifier for the particular global resource. Only if none of the accessed local resources contain such an identifier, is the instruction issued and the thread allowed to write to the global resource. Otherwise, the instruction is blocked and an exception may be raised to alert the program that issued the instruction that the write failed.Type: GrantFiled: February 28, 2013Date of Patent: March 31, 2015Assignee: Imagination Technologies LimitedInventors: Guixin Wang, Hugh Jackson, Robert Graham Isherwood
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Publication number: 20150058574Abstract: Methods of increasing the efficiency of memory resources within a processor are described. In an embodiment, instead of including dedicated DSP indirect register resource for storing data associated with DSP instructions, this data is stored in an allocated and locked region within the cache. The state of any cache lines which are used to store DSP data is then set to prevent the data from being written to memory. The size of the allocated region within the cache may vary according to the amount of DSP data that needs to be stored and when no DSP instructions are being run, no cache resources are allocated for storage of DSP data.Type: ApplicationFiled: August 11, 2014Publication date: February 26, 2015Inventors: Jason Meredith, Robert Graham Isherwood, Hugh Jackson
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Publication number: 20150012728Abstract: The invention is a method and system for providing trace data in a pipelined data processor. Aspects of the invention include providing a trace pipeline in parallel to the execution pipeline, providing trace information on whether conditional instructions complete or not, providing trace information on the interrupt status of the processor, replacing instructions in the processor with functionally equivalent instructions that also produce trace information and modifying the scheduling of instructions in the processor based on the occupancy of a trace output buffer.Type: ApplicationFiled: May 7, 2014Publication date: January 8, 2015Applicant: IMAGINATION TECHNOLOGIES LIMITEDInventors: Robert Graham Isherwood, Ian Oliver, Andrew David Webber
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Patent number: 8775875Abstract: The invention is a method and system for providing trace data in a pipelined data processor. Aspects of the invention including providing a trace pipeline in parallel to the execution pipeline, providing trace information on whether conditional instructions are complete or not, providing trace information on the interrupt status of the processor, replacing instructions in the processor with functionally equivalent instructions that also produce trace information and modifying the scheduling of instructions in the processor based on the occupancy of the trace output buffer.Type: GrantFiled: April 28, 2009Date of Patent: July 8, 2014Assignee: Imagination Technologies, LimitedInventors: Robert Graham Isherwood, Ian Oliver, Andrew Webber
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Publication number: 20140068232Abstract: Global register protection in a multi-threaded processor is described. In an embodiment, global resources within a multi-threaded processor are protected by performing checks, before allowing a thread to write to a global resource, to determine whether the thread has write access to the particular global resource. The check involves accessing one or more local control registers or a global control field within the multi-threaded processor and in an example, a local register associated with each other thread in the multi-threaded processor is accessed and checked to see whether it contains an identifier for the particular global resource. Only if none of the accessed local resources contain such an identifier, is the instruction issued and the thread allowed to write to the global resource. Otherwise, the instruction is blocked and an exception may be raised to alert the program that issued the instruction that the write failed.Type: ApplicationFiled: February 28, 2013Publication date: March 6, 2014Applicant: IMAGINATION TECHNOLOGIES LIMITEDInventors: Guixin WANG, Hugh Jackson, Robert Graham Isherwood
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Publication number: 20130219145Abstract: A multithreaded processor can concurrently execute a plurality of threads in a processor core. The threads can access a shared main memory through a memory interface; the threads can generate read and write transactions that cause shared main memory access. An incoherency detection module prevents incoherency by maintaining a record of outstanding global writes, and detecting a conflicting global read. A barrier is sequenced with the conflicting global write. The conflicting global read is allowed to proceed after the sequence of the conflicting global write and the barrier are cleared. The sequence can be maintained by a separate queue for each thread of the plurality.Type: ApplicationFiled: July 23, 2012Publication date: August 22, 2013Applicant: Imagination Technologies, Ltd.Inventors: Robert Graham Isherwood, Yin Nam Ko
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Patent number: 8234455Abstract: An apparatus for controlling memory access in a multithreaded processor supporting a plurality of threads is provided. The apparatus includes a processor core; a cache memory storing data accessible by each of the plurality of threads; a main memory storing data accessible by a plurality of threads; an incoherency detection module; and a memory arbiter. The incoherency detection module is connected between the processor core and the memory arbiter, and the memory arbiter is connected between the incoherency detection module and the main memory. There is a separate request queue for each thread for read and write requests sent from the cache memory to the memory arbiter. The incoherency detection module stores an indication of a memory address for each write request sent from the cache memory to the main memory in a write address memory, and compares the address of each subsequent read request sent from the cache memory with indications in the write address memory.Type: GrantFiled: September 25, 2009Date of Patent: July 31, 2012Assignee: Imagination Technologies LimitedInventors: Robert Graham Isherwood, Yin Nam Ko
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Publication number: 20100257322Abstract: There is provided an apparatus for controlling memory access in a multithreaded processor supporting a plurality of threads, comprising: a processor core; a cache memory storing data accessible by each of the plurality of threads; a main memory storing data accessible by a plurality of threads; an incoherency detection module; and a memory arbiter, wherein the incoherency detection module is connected between the processor core and the memory arbiter, and the memory arbiter is connected between the incoherency detection module and the main memory and wherein there is a separate request queue for each thread for read and write requests sent from the cache memory to the memory arbiter; wherein, in use, the incoherency detection module stores an indication of a memory address for each write request sent from the cache memory to the main memory in a write address memory, and compares the address of each subsequent read request sent from the cache memory with indications in the write address memory and, if the addType: ApplicationFiled: September 25, 2009Publication date: October 7, 2010Inventors: Robert Graham Isherwood, Yin Nam Ko
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Patent number: 7712101Abstract: A method and apparatus are provided for dynamically allocating an access bandwidth for one or more resources to threads of a multithreaded processor. The allocation is performed by providing an execution based metric for each thread and providing an access to the resource in dependence on the execution based metrics of the threads. In addition, or alternatively, a resource based metric can be determined and the access to the resource is provided in dependence on the resource based metric.Type: GrantFiled: September 24, 2004Date of Patent: May 4, 2010Assignee: Imagination Technologies LimitedInventors: Yin Nam Ko, Robert Graham Isherwood
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Publication number: 20090287907Abstract: The invention is a method and system for providing trace data in a pipelined data processor. Aspects of the invention include providing a trace pipeline in parallel to the execution pipeline, providing trace information on whether conditional instructions complete or not, providing trace information on the interrupt status of the processor, replacing instructions in the processor with functionally equivalent instructions that also produce trace information and modifying the scheduling of instructions in the processor based on the occupancy of a trace output buffer.Type: ApplicationFiled: April 28, 2009Publication date: November 19, 2009Inventors: Robert Graham Isherwood, Ian Oliver, Andrew Webber