Abstract: The invention is a system and a device for use in open or minimally invasive surgical procedures, such as a bone implant fixation procedure. The device is configured to perform various functions during a bone implant fixation procedure, including performing at least one of: penetration of a bone to form a hole or opening for receipt of a screw; neuromonitoring, in cooperation with a neuromonitoring device, of the hole during, or post-, formation of the hole so as to sense any nearby nerves adjacent to the hole that may be in the path of a screw, or otherwise affected, when a screw is placed within the hole; neurostimulation, in cooperation with a neuromonitoring device, of nerves adjacent to the hole during, or post-, formation of the hole; and measuring of a depth of the hole and providing a digital measurement of the depth to assist the surgeon in selecting the appropriate length of screw.

Abstract: A system, method, and apparatus for concealing searches for information stored on public networks, includes splitting of a search query, transforming the query into one or more related queries, and searching each of related queries separately.

Abstract: An I/O controller for a computer system having a plurality of memory devices of different types such as floppy and hard disks, whereinn a single cache memory is employed for all of the memory devices. Each of the memory devices is provided with its own interface device which directs data outputted from the associated memory device onto a common device bus. From the device bus data is transferred to a cache memory via a separate cache bus, and then to a system processor via the same cache bus. Memory space within the cache memory may be allocated among the various memory devices.

Abstract: A redundant error-detecting addressing code for use in a cache memory. A directory converts logical data addresses to physical addresses in the cache where the data is stored in blocks. The blocks are expanded to include redundant addressing information such as the logical data address and the physical cache address. When a block is accessed from the cache, the redundant addressing is compared to the directory addressing information to confirm that the correct data has been accessed.

Abstract: A method and apparatus for performing data base searches in which the host processor and main memory are free for other processing tasks between the time that the host processor requests the search until the search results are reported back to the host processor. To commence the search, an input/output controller communicates from the host processor to a record scan circuit values of a skip length, a key length and a data length. While data records are received serially from disk files, within each data record, a length of data equal to the specified skip length is initially skipped. Following this, a search argument is compared with a length of data specified by the key length value. This comparison operation is alternated with skipping of data specified by the data length value until the end of the record is reached or until a specified number of comparisons has taken place. The data record is stored as it is received from the files.

Abstract: Serial storage interface apparatus for coupling a serial storage mechanism, such as a charge coupled storage device or a magnetic bubble storage device, to a data processor input/output (I/O) bus. Speed control circuitry is provided for causing the serial storage mechanism to operate at a higher speed when the data processor is responding more rapidly to data transfer requests from the interface apparatus and at a lower speed when the data processor is responding less rapidly to data transfer requests from the interface apparatus. This speed adjustment feature reduces the amount of data buffering required for interfacing a serial storage mechanism to an asynchronous variable response time I/O bus system.