Abstract: Current sensing with RDSON correction is disclosed. In an embodiment, a method comprises: measuring an approximate temperature of a MOS transistor switch by a temperature sensor to yield a measured temperature; calculating a corrected temperature from the measured temperature using a stored temperature sensor gain and offset correction function; measuring a gate drive voltage for the MOS transistor; calculating a voltage correction factor using a stored voltage correction function, wherein the stored voltage correction function is a function of the corrected temperature and the gate drive voltage; measuring a RDSON voltage drop across the MOS transistor switch to yield a measured RDSON voltage drop; and calculating the current using the measured RDSON drop and the voltage correction factor.

Abstract: Systems and methods for digital voltage compensation in a power supply integrated circuit are provided. In at least one embodiment, a method comprises receiving a digital voltage code, the digital voltage code corresponding to an output voltage value; setting an output count on a first counter to change from a present first digital count corresponding to a present voltage code value toward a target first digital count corresponding to a new voltage code value; and setting a second count to an offset count value on a second counter when the new voltage code value is received. The method also comprises combining the second count with the output count to form a combined count value; and decrementing the second count value from the offset count value to zero when the first counter reaches the target first digital count.

Abstract: Current sensing with RDSON correction is disclosed. In an embodiment, a method comprises: measuring an approximate temperature of a MOS transistor switch by a temperature sensor to yield a measured temperature; calculating a corrected temperature from the measured temperature using a stored temperature sensor gain and offset correction function; measuring a gate drive voltage for the MOS transistor; calculating a voltage correction factor using a stored voltage correction function, wherein the stored voltage correction function is a function of the corrected temperature and the gate drive voltage; measuring a RDSON voltage drop across the MOS transistor switch to yield a measured RDSON voltage drop; and calculating the current using the measured RDSON drop and the voltage correction factor.

Abstract: Current sensing with RDSON correction is disclosed. In an embodiment, a method comprises: measuring an approximate temperature of a MOS transistor switch by a temperature sensor to yield a measured temperature; calculating a corrected temperature from the measured temperature using a stored temperature sensor gain and offset correction function; measuring a gate drive voltage for the MOS transistor; calculating a voltage correction factor using a stored voltage correction function, wherein the stored voltage correction function is a function of the corrected temperature and the gate drive voltage; measuring a RDSON voltage drop across the MOS transistor switch to yield a measured RDSON voltage drop; and calculating the current using the measured RDSON drop and the voltage correction factor.

Abstract: Current sensing with RDSON correction is disclosed. In an embodiment, a method comprises: measuring an approximate temperature of a MOS transistor switch by a temperature sensor to yield a measured temperature; calculating a corrected temperature from the measured temperature using a stored temperature sensor gain and offset correction function; measuring a gate drive voltage for the MOS transistor; calculating a voltage correction factor using a stored voltage correction function, wherein the stored voltage correction function is a function of the corrected temperature and the gate drive voltage; measuring a RDSON voltage drop across the MOS transistor switch to yield a measured RDSON voltage drop; and calculating the current using the measured RDSON drop and the voltage correction factor.

Abstract: Systems and methods for digital voltage compensation in a power supply integrated circuit are provided. In at least one embodiment, a method comprises receiving a digital voltage code, the digital voltage code corresponding to an output voltage value; setting an output count on a first counter to change from a present first digital count corresponding to a present voltage code value toward a target first digital count corresponding to a new voltage code value; and setting a second count to an offset count value on a second counter when the new voltage code value is received. The method also comprises combining the second count with the output count to form a combined count value; and decrementing the second count value from the offset count value to zero when the first counter reaches the target first digital count.

Abstract: Systems and methods for digital voltage compensation in a power supply integrated circuit are provided. In at least one embodiment, a method includes receiving a digital voltage code, the digital voltage code corresponding to an output voltage value; setting an output count on a first counter to change from a present first digital count corresponding to a present voltage code value toward a target first digital count corresponding to a new voltage code value; and setting a second count to an offset count value on a second counter when the new voltage code value is received. The method also includes combining the second count with the output count to form a combined count value; and decrementing the second count value from the offset count value to zero when the first counter reaches the target first digital count.

Abstract: Current sensing with RDSON correction is disclosed. In an embodiment, a method comprises: measuring an approximate temperature of a MOS transistor switch by a temperature sensor to yield a measured temperature; calculating a corrected temperature from the measured temperature using a stored temperature sensor gain and offset correction function; measuring a gate drive voltage for the MOS transistor; calculating a voltage correction factor using a stored voltage correction function, wherein the stored voltage correction function is a function of the corrected temperature and the gate drive voltage; measuring a RDSON voltage drop across the MOS transistor switch to yield a measured RDSON voltage drop; and calculating the current using the measured RDSON drop and the voltage correction factor.

Abstract: A voltage regulator integrated circuit comprises a control circuit driving at least one power switch to provide a regulated voltage at an output of an inductor/capacitor (LC) circuit coupled to the at least one power switch; an error amplifier having a first input coupled to a feedback signal representative of the regulated output voltage and a second input coupled to a reference signal; and a compensation network coupled to an output of the error amplifier and configured to provide a compensation voltage. The compensation network includes at least one digitally programmable resistor array and at least one digitally programmable capacitor array. Each array provides a plurality of user selectable component values. The control circuit includes a pulse modulator configured to modulate an input voltage based on the compensation voltage.

Abstract: Systems and methods for digital voltage compensation in a power supply integrated circuit are provided. In at least one embodiment, a method comprises receiving a digital voltage code, the digital voltage code corresponding to an output voltage value; setting an output count on a first counter to change from a present first digital count corresponding to a present voltage code value toward a target first digital count corresponding to a new voltage code value; and setting a second count to an offset count value on a second counter when the new voltage code value is received. The method also comprises combining the second count with the output count to form a combined count value; and decrementing the second count value from the offset count value to zero when the first counter reaches the target first digital count.

Abstract: Systems and methods for digital voltage compensation in a power supply integrated circuit are provided. In at least one embodiment, a method includes receiving a digital voltage code, the digital voltage code corresponding to an output voltage value; setting an output count on a first counter to change from a present first digital count corresponding to a present voltage code value toward a target first digital count corresponding to a new voltage code value; and setting a second count to an offset count value on a second counter when the new voltage code value is received. The method also includes combining the second count with the output count to form a combined count value; and decrementing the second count value from the offset count value to zero when the first counter reaches the target first digital count.

Abstract: An apparatus for sensing an input current through an inductor includes an RC circuit connected in parallel with the inductor across first and second input pins of an integrated circuit. A voltage monitoring circuit monitors a first voltage at the first input pin of the integrated circuit and monitors a second voltage at the second input pin of the integrated circuit. An op-amp compares the first voltage with the second voltage and generates a control output responsive to the comparison. A current sink circuit responsive to the indication controls the first voltage to substantially equal the second voltage.

Abstract: A voltage regulator integrated circuit comprises a control circuit driving at least one power switch to provide a regulated voltage at an output of an inductor/capacitor (LC) circuit coupled to the at least one power switch; an error amplifier having a first input coupled to a feedback signal representative of the regulated output voltage and a second input coupled to a reference signal; and a compensation network coupled to an output of the error amplifier and configured to provide a compensation voltage. The compensation network includes at least one digitally programmable resistor array and at least one digitally programmable capacitor array. Each array provides a plurality of user selectable component values. The control circuit includes a pulse modulator configured to modulate an input voltage based on the compensation voltage.

Abstract: Systems and methods for digital voltage compensation in a power supply integrated circuit are provided. In at least one embodiment, a method comprises receiving a digital voltage code, the digital voltage code corresponding to an output voltage value; setting an output count on a first counter to change from a present first digital count corresponding to a present voltage code value toward a target first digital count corresponding to a new voltage code value; and setting a second count to an offset count value on a second counter when the new voltage code value is received. The method also comprises combining the second count with the output count to form a combined count value; and decrementing the second count value from the offset count value to zero when the first counter reaches the target first digital count.

Abstract: A voltage regulator integrated circuit comprises a control circuit driving at least one power switch to provide a regulated voltage at an output of an inductor/capacitor (LC) circuit coupled to the at least one power switch; an error amplifier having a first input coupled to a feedback signal representative of the regulated output voltage and a second input coupled to a reference signal; and a compensation network coupled to an output of the error amplifier and configured to provide a compensation voltage. The compensation network includes at least one digitally programmable resistor array and at least one digitally programmable capacitor array. Each array provides a plurality of user selectable component values. The control circuit includes a pulse modulator configured to modulate an input voltage based on the compensation voltage.

Abstract: A voltage regulator integrated circuit comprises a control circuit driving at least one power switch to provide a regulated voltage at an output of an inductor/capacitor (LC) circuit coupled to the at least one power switch; an error amplifier having a first input coupled to a feedback signal representative of the regulated output voltage and a second input coupled to a reference signal; and a compensation network coupled to an output of the error amplifier and configured to provide a compensation voltage. The compensation network includes at least one digitally programmable resistor array and at least one digitally programmable capacitor array. Each array provides a plurality of user selectable component values. The control circuit includes a pulse modulator configured to modulate an input voltage based on the compensation voltage.

Abstract: An integrated circuit is configured to be coupled to a current sensing element and a set resistor having a resistance Rset. The integrated circuit comprises a sense resistor having a resistance Rsense. The sense resistor is coupled to an input of the integrated circuit such that a first sensed current from the current sensing element flows through the sense resistor. The integrated circuit also comprises a reference resistor having a resistance Rreference which is a fixed multiple of Rsense; and circuitry configured to produce an output current such that the value of the output current is proportional to a value of Rset and a fixed ratio between Rsense and Rreference.

Abstract: An adaptive pulse positioning modulator including a sense circuit which provides a compensation signal indicative of output voltage error, a filter circuit having an input receiving the compensation signal and an output providing an adjust signal, a leading ramp circuit which provides a repetitive first leading edge ramp signal having a slope which is adjusted by the adjust signal, a comparator circuit which provides a first start trigger signal when the first leading edge ramp signal reaches the compensation signal and a first end trigger signal when a first trailing edge ramp signal reaches the compensation signal, a trailing ramp circuit which initiates ramping of the first trailing edge ramp signal when the first start trigger signal is provided, and a pulse control logic which asserts pulses on a PWM signal based on the trigger signals.

Abstract: A DC/DC converter has an output voltage and sources an output current to a load. The DC/DC converter includes an error amplifier with a reference input and a summing input. The reference input is electrically connected to a reference voltage. The summing input is electrically connected to the output voltage and the output current. The summing input is configured for adding together the output voltage and the output current. The error amplifier issues an error signal and adjusts the error signal dependent at least in part upon the output voltage and the output current. A comparator receives the error signal. The comparator has a ramp input electrically connected to a voltage ramp signal. The comparator issues an output signal that is based at least in part upon said error input. A power switch has an on condition and an off condition, and supplies dc current to the load when in the on condition. The power switch has a control input electrically connected to the comparator output signal.

Abstract: An adaptive pulse positioning modulator including a sense circuit which provides a compensation signal indicative of output voltage error, a filter circuit having an input receiving the compensation signal and an output providing an adjust signal, a leading ramp circuit which provides a repetitive first leading edge ramp signal having a slope which is adjusted by the adjust signal, a comparator circuit which provides a first start trigger signal when the first leading edge ramp signal reaches the compensation signal and a first end trigger signal when a first trailing edge ramp signal reaches the compensation signal, a trailing ramp circuit which initiates ramping of the first trailing edge ramp signal when the first start trigger signal is provided, and a pulse control logic which asserts pulses on a PWM signal based on the trigger signals.